• 150 mm × 150 mm board outline
• Four-layer stackup established
• Through-hole components placed on the top side
• Zero reported overlapping-copper errors
• Zero reported floating copper
• Zero reported dangling traces
• Route all 14 remaining airwires
• Run fresh full PCB DRC
• Run fresh schematic ERC
• Complete BOM/MPN audit
• Pass final manufacturing review

Treat the trace IDs below as a stop-point record. Regenerate the airwire report before editing because IDs and counts can change after any routing operation.

• Confirm no layout/routing job is still active in the background.
• Save or note the current clean-copper revision so it can be restored if routing creates shorts.
• Run a fresh airwire-only DRC and reconcile its results against this list.
• Preserve the 150 mm × 150 mm outline, mounting holes, connector edge access, and top-side through-hole placement.
• Do not use broad autorouting unless it can preserve the current zero-overlap state.

• Trace 5bab — previously associated with MEGA_D2_M1_RPWM; expected endpoints J80:Pin_3 ↔ J90:Pin_1. Verify live net and pads before routing.
• Trace 3b3c — endpoint mapping not recorded. Identify the net and both pads from the fresh DRC/layout data before routing.
• Trace fc6b — previously associated with MEGA_D11_TB_DIR; expected endpoints J30:4 ↔ J92:Pin_2. Verify before routing.
• Trace 7022 — previously associated with MEGA_D11_TB_DIR; expected endpoints J30:4 ↔ J92:Pin_2. This may be another disconnected segment of the same net; inspect the complete route before adding copper.
• Trace d2e1 — previously associated with MEGA_D2_M1_RPWM; expected endpoints J80:Pin_3 ↔ J90:Pin_1. Verify before routing.
• Trace 43c1 — previously associated with MEGA_D2_M1_RPWM; expected endpoints J80:Pin_3 ↔ J90:Pin_1. Verify before routing.
• Trace ffd2 — previously associated with MEGA_D11_TB_DIR; expected endpoints J30:4 ↔ J92:Pin_2. Verify before routing.
• Trace 9aa3 — endpoint mapping not recorded. Identify the net and both pads before routing.
• Trace 1734 — previously associated with MEGA_D2_M1_RPWM; expected endpoints J80:Pin_3 ↔ J90:Pin_1. Verify before routing.
• Trace e2c6 — endpoint mapping not recorded. Identify the net and both pads before routing.
• Trace a64e — endpoint mapping not recorded. Identify the net and both pads before routing.
• Trace 7f61 — previously associated with MEGA_A7_M2_RIS; expected endpoints J83:Pin_3 ↔ J89:Pin_4. Verify before routing.
• Trace eb0c — endpoint mapping was unavailable. Identify the net and both pads before routing.
• Trace d3d4 — previously associated with MEGA_D5_M2_LPWM; expected endpoints J82:Pin_4 ↔ J90:Pin_4. Verify before routing.

• Airwire count is exactly zero.
• No trace was assigned to the wrong net.
• No different-net copper overlaps were introduced.
• No trace-to-pad, trace-to-via, via-to-pad, or board-edge clearance errors remain.
• High-current 24 V, 12 V, 6 V servo, and GND routes retain appropriate width/copper area.
• Signal routes do not neck down or interrupt high-current paths.
• No copper crosses mounting-hole keepouts.
• Screw-terminal pads remain accessible and are not thermally starved.

• Airwires: zero
• Different-net overlapping copper: zero
• Overlapping traces: zero
• Floating copper: zero, or individually reviewed and intentionally accepted
• Dangling traces: zero
• Missing footprints: zero
• Invalid-layer objects: zero
• Copper/board-edge clearance violations: zero
• Copper/mounting-hole clearance violations: zero
• Annular-ring and drill-size violations: zero
• Silkscreen over pads or board edge: zero
• Component courtyard/body overlaps: zero
• All components remain fully inside the board outline
• Four-layer stackup is still present and correctly ordered
• Confirm intended inner-layer copper/planes and return paths rather than assuming the stackup created them

• Run fresh schematic ERC.
• Resolve all true unconnected-pin and conflicting-driver errors.
• Confirm all 24 V, 12 V, 6 V servo, 5 V, and GND terminal groups connect to their intended rails.
• Confirm the 12 V, 6 V, and 5 V bucks are external modules and their input/output polarity terminals are unambiguous.
• Confirm all BTS7960 control and current-sense signals match the intended Mega pins.
• Confirm TB6600 STEP, DIR, and enable/common wiring matches the selected interface convention.
• Confirm three relay inputs and relay-module power connections.
• Confirm all four MG996R servo signal/power/ground terminal groups use the 6 V servo rail, not Arduino 5 V.
• Confirm all four HC-SR04 terminal groups have 5 V, GND, TRIG, and ECHO.
• Confirm all three DS18B20 data nets have independent 4.7 kΩ pull-ups to 5 V.
• Confirm all five potentiometers have 5 V, GND, and separate analog-wiper nets.
• Confirm every external module and the Mega share the intended common ground.
• Mark intentionally unused terminals/pins explicitly rather than leaving ambiguous ERC warnings.

• Export or inspect a fresh BOM and count every line with a blank MPN.
• Confirm all screw terminals retain verified manufacturer, MPN, pitch, position count, current rating, and through-hole footprint.
• Confirm mounting holes and net portals are correctly excluded from procurement where appropriate.
• Consolidate duplicate BOM rows only when value, voltage rating, tolerance, package, and manufacturer part are identical.

• Verify resistance value.
• Verify tolerance; use 1% unless the circuit explicitly allows otherwise.
• Verify power rating; normally at least 0.25 W for signal/pull-up roles.
• Verify axial lead spacing and body size match the PCB footprint.
• Verify flameproof/fusible requirements for any resistor exposed to a power rail.
• Confirm the three DS18B20 pull-ups are 4.7 kΩ and individually connected.

• Verify capacitance for every capacitor.
• Verify voltage rating with margin: use at least 35 V on the 24 V rail, at least 25 V on the 12 V rail, and at least 10 V on 5–6 V rails unless a higher documented requirement applies.
• Verify polarized versus non-polarized type.
• Verify electrolytic diameter, height, and lead spacing match the PCB footprint.
• Verify temperature rating; prefer 105 °C electrolytics for power distribution.
• Verify ripple-current rating for bulk capacitors near buck outputs and servo loads.
• Verify polarity markings are clear on both schematic and silkscreen.

• Assign actual external buck-converter models and ratings to the assembly documentation:
  • 24 V → 12 V, sized from measured/verified motor and pump current
  • 24 V → 6 V, at least 15 A recommended for four MG996R servos
  • 24 V → 5 V, approximately 3–5 A depending on Mega, sensors, and relay-module demand
• Record PSU voltage/current rating.
• Select main and branch fuse types/ratings only after motor stall, pump startup, and stepper-driver input currents are known.
• Verify terminal current ratings exceed the protected branch currents.
• Add all off-board items needed for assembly to a supplemental BOM: fuses/holders, buck converters, wire, ferrules, spacers, screws, and mating labels.

• Every fitted electrical component has a value and footprint.
• Every non-generic component has manufacturer and MPN.
• Every generic passive has sufficient value/rating/package data for unambiguous purchasing.
• No obsolete, unavailable, or minimum-order-only part is used without an approved substitute.
• Quantities match the schematic and physical PCB.
• DNI/non-fitted parts are explicitly marked.

• Full DRC passes with zero airwires, shorts, missing footprints, and invalid-layer objects.
• ERC passes or every remaining warning is documented and intentionally accepted.
• Board outline is closed and measures 150 mm × 150 mm or less.
• Drill sizes and annular rings are compatible with the chosen fabricator.
• Copper weight and finished-board current assumptions are documented; high-current loads must not exceed verified PCB/terminal capacity.
• Gerbers and drill files are generated and visually reviewed in an independent viewer.
• BOM is exported and manually checked.
• Pick-and-place is optional for this through-hole-focused board; confirm assembly method with the manufacturer.
• IPC-D-356/netlist electrical-test file is generated if supported by the selected fab.
• Verify connector labels, voltage labels, polarity, pin numbering, and external fuse warnings on final silkscreen.
• Perform continuity and isolation tests on the first unpowered assembled board.
• Bring up one power rail and one load group at a time using current-limited supplies where possible.

• DC motor running and stall current
• Pump running and startup current
• TB6600 supply/input current at the chosen stepper current setting
• Exact external buck-converter models
• PCB copper weight and manufacturer capability
• Desired fabrication/assembly vendor

• Cleared stale job auto-layout-d4fe548e-180f-41a0-9149-9a5f34864dd2 after confirming outOfCredit; accepted persisted routing remained intact.
• A fresh autoroute added 90 routing nodes but produced 38 different-net overlapping-copper errors and four dangling-trace warnings. Commit #6bbe1552 was atomically reverted to #a18bdef3, restoring the clean-copper baseline.
• Targeted routing of MEGA_D2_M1_RPWM (J80:Pin_3 ↔ J90:Pin_1) then failed internally with Cannot read properties of undefined (reading 'active'); no targeted change was accepted.
• Final fresh DRC at 09:58 UTC reports exactly 14 airwire errors and no other returned DRC categories. Final fresh schematic ERC reports no findings.
• Retained 53 verified Würth terminals with MPNs 691137710002/003/004/006.
• C9–C12 now specify datasheet-verified Kyocera AVX SR215E104MARTR1 (100 nF, 50 V, Z5U, ±20%, radial THT, 5.08 mm pitch). Values and footprints were unchanged.
• R1–R3 retain 4.7 kΩ, 1%, 0.25 W, axial P7.62/D2.5 requirements. C1–C8 retain values, ratings, and footprints with controlled-substitution sourcing fields; exact electrolytic MPNs remain open pending mechanical/ripple verification.
• Export gate failed due to 14 airwires, so Gerber, BOM export, IPC-D-356, and pick-and-place were not generated.
• No high-current approval is claimed. Motor, pump, TB6600, PSU, buck, fuse, copper-weight, and trace/via current evidence remain required.

• Live PCB state: 150 mm × 150 mm rounded rectangle, four copper layers, 68 physical footprints/components, all on Top; existing edge-oriented connector placement preserved.
• Routing preflight: board valid; 68 components and 47 nets; no routing-feasibility anomalies.
• Pre-routing cleanup/full DRC categories: zero reported dangling traces, floating copper, missing footprints, invalid-layer objects, overlapping copper/fills/traces, pad-access violations, component-body overlap, and outside-board components.
• Airwire DRC: 14 errors remain: Trace 5bab, 3b3c, fc6b, 7022, d2e1, 43c1, ffd2, 9aa3, 1734, e2c6, a64e, 7f61, eb0c, d3d4.
• Targeted routing was attempted on three previously mapped signal connections. The generated routes introduced different-net copper-overlap errors, so all three route commits were atomically reverted. Post-revert DRC restored the prior zero-overlap state and the 14-airwire baseline.
• Full autoroute could not start because the existing auto-layout job auto-layout-d4fe548e-180f-41a0-9149-9a5f34864dd2 is outOfCredit. It was not cancelled, to avoid discarding paid routing work.
• Live schematic ERC category review returned no reported ERC findings. Net inspection confirms separate 24V, 12V, 6V_SERVO, and 5V rails plus common GND. R1/R2/R3 are each 4.7 kΩ and independently connect DS18B20 data nets D37/D38/D39 to 5V.
• BOM live inventory: 68 fitted parts in 6 BOM groups: 53 verified Würth WR-TBL screw terminals (MPNs 691137710002/003/004/006), 12 generic THT capacitors, and 3 generic THT resistors.
• Generic resistors are unambiguous for value/fit: 4.7 kΩ, 1%, 0.25 W, axial P7.62/D2.5, separate DS18B20 pull-ups. Exact purchasable resistor MPNs and temperature ratings remain unset.
• Generic capacitors have values, polarity/type, voltage ratings, and THT footprints recorded. Temperature rating, tolerance, ripple-current rating, body-height confirmation, exact purchasable MPN, and final silkscreen polarity inspection remain open. These were not guessed.
• Safety blockers remain: verified motor running/stall current, pump running/startup current, TB6600 input current at selected setting, PSU rating, exact external buck models, fuse types/ratings, copper weight/fabricator stackup capability, and resulting trace/via/terminal current-capacity approval.