F4
VDD
F2
P_CBE_L[2]
GPIO[3]
VDD
T4
M3
VDD
VDD
E1
VDD
S_AD[7]
R8
C2
S_STOP_L
VDD
VDD
MS1
VDD
S_AD[1]
S_AD[8]
VDD
GPIO[1]
N1
M2
VDD
P_PERR_L
VDD
VDD
K2
P5
M16
P_CBE_L[0]
P_DEVSEL_L
S_SERR_L
N15
VDD
R7
VDD
P_VIO
S_AD[25]
L13
L4
VDD
VDD
P_REQ_L
GPIO[0]
A1
VDD
M14
VDD
S_AD[0]
S_AD[12]
T14
L3
VDD
T9
S_AD[3]
S_AD[4]
S_AD[23]
T2
T5
F3
A12
VDD
G3
T6
VDD
S_AD[18]
S_AD[26]
VDD
S_AD[28]
VDD
S_AD[10]
L16
RESERVED
S_AD[21]
E15
D15
B12
S_RESET_L
T8
M13
VDD
VDD
VDD
VDD
P_RESET_L
S_AD[19]
TDI
L15
P_IRDY_L
VDD
S_AD[29]
L14
BPCCE
S_AD[14]
H3
P_STOP_L
E2
B4
VDD
B3
VDD
S_TRDY_L
A2
T15
P_SERR_L
K3
P7
P_CBE_L[1]
P_PAR
VDD
E4
CFG66/SCAN_EN_H/CLK_RATE
S_AD[13]
N5
N12
C11
P8
GPIO[2]
VDD
N3
D3
A13
P_M66EN
L1
R5
VDD
G1
MSK_IN/ASYNC_CLK_IN
MS0
R13
P16
P_CLK
VDD
R12
T7
M15
L2
VDD
A11
S_AD[30]
A10
S_AD[9]
TDO
VDD
P_FRAME_L
P_LOCK_L
TRST_L
VDD
B9
TCK
B6
VDD
S_VIO
S_AD[2]
P_TRDY_L
S_AD[16]
VDD
VDD
S_AD[11]
F1
H2
D2
P_CBE_L[3]
S_AD[5]
N6
RESERVED
S_AD[20]
VDD
VDD
VDD
B10
S_AD[6]
M1
VDD
S_AD[22]
P12
VDD
TMS
P_GNT_L
S_AD[27]
VDD
P_IDSEL
S_AD[17]
D1
C1
E3
S_AD[24]
VDD
S_AD[31]
S_AD[15]
PI7C8150BNDIE