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D1_MDQ[45]
SD1_TX[0]
GND
SD1_RX[2]
OVDD
TSEC_1588_TRIG_IN
GVDD
D1_MDQ[61]
GVDD
AE14
D1_MDQ[39]
D1_MCS[1]#
AH5
J20
D2_MDQS[5]
A24
D2_MDQS[4]
D1_MDQ[42]
GND
SD1_TX[4]
TSEC1_TXD[0]/FIFO1_TXD[0]
GVDD
J30
D2_MA[8]
GVDD
GND
DMA1_DDONE[1]#
J15
SD1_TX[0]#
D2_MDQ[13]
AD4
AC31
GVDD
D2_MA[4]
GND
AK5
AE1
LVDD
D2_MWE#
D1_MCK[0]#
D2_MDQS[8]
F8
H20
Y23
P25
A31
GVDD
AF7
W5
B32
D2_MCKE[0]
OVDD
N18
H15
M20
D2_MDQS[6]#
AM31
GND
D2_MDQ[23]
D1_MDQ[30]
D2_MA[5]
D2_MA[2]
AB2
LGPL1/LFALE
EC_GTX_CLK125
A10
D2_MCK[0]
AH27
XVDD_SRDS2
N24
AH26
D1_MDQ[18]
D1_MDQ[3]
M22
Y21
GND
D1_MDQ[12]
D2_MDQS[4]#
LGPL3/LFWP
GVDD
D1_MDQ[52]
AM9
Reserved
IRQ[3]
R8
D1_MDQ[37]
AM13
AK17
GVDD
D1_MDQ[38]
H4
GVDD
AJ31
D2_MDM[7]
GND
AD13
J17
K21
AD8
AL6
DMA2_DREQ[2]
D1_MCK[5]
D1_MODT[3]
D1_MDQ[60]
B31
GVDD
D1_MDQ[55]
G11
EC3_MDIO
GVDD
SD1_TX[5]
J5
AE3
SD1_TX[7]
EC5_MDC
AB3
E16
AK16
V10
U29
F20
AE25
TVDD
GND
AJ23
SD1_TX[1]
DMA1_DREQ[1]#
B30
SD1_TX[6]
D2_MDQ[10]
DMA1_DREQ[0]#
AF16
SD1_RX[4]
D19
LGPL4/LGTA/LUPWAIT/LPBSE/LFRB
AH23
H12
J31
GVDD
N1
GND
AH30
H19
UART_CTS[0]#
U28
D2_MDM[3]
IIC2_SDA
D1_MDQ[1]
GND
AF30
R5
GND
GND
GND
GND
SVDD_SRDS1
AH20
G18
IRQ[0]
D2_MDM[4]
IRQ[5]
GND
AK27
GND
D1_MDQ[4]
LSYNC_OUT
UDE1#
IRQ[1]
GND
GND
TSEC_1588_TRIG_OUT
D2_MCK[1]
XVDD_SRDS1
D17
GVDD
GND
J14
GVDD
D1_MDQ[26]
XVDD_SRDS1
UART_CTS[1]#
TSEC1_RXD[4]/FIFO1_RXD[4]
AM1
T32
D2_MDQ[17]
M9
GVDD
D1_MODT[1]
GVDD
SD1_RX[3]
GVDD
TSEC_1588_CLK
E21
D1_MODT[0]
OVDD
AG24
GVDD
GND
AG31
GVDD
AE18
XVDD_SRDS2
Reserved
D1_MDQ[14]
P10
D22
AG1
GND
C10
P28
AC19
GVDD
AG16
D2_MCK[5]
AF20
OVDD
D1_MCKE[0]
D2_MDQ[14]
GND
GVDD
AC12
XVDD_SRDS2
OVDD
L11
GVDD
J2
U26
D2_MCKE[1]
GVDD
D2_MA[14]
D1_MCK[1]
AG20
TSEC_1588_CLK_OUT
SD1_TX[4]#
U27
XVDD_SRDS1
TSEC1_RXD[1]/FIFO1_RXD[1]
EC1_MDC
W2
GVDD
D1_MDQ[59]
XVDD_SRDS1
H17
E6
Reserved
SD1_RX[6]
GND
AF22
L12
D2_MDQ[4]
D2_MA[11]
GND
GVDD
XVDD_SRDS2
GND
TSEC1_TXD[2]/FIFO1_TXD[2]
L7
GND
AB20
GND
TSEC1_TXD[1]/FIFO1_TXD[1]
GVDD
GVDD
D2_MRAS
W8
C16
GVDD
GND
LGPL5
C14
AH32
D2_MDQ[9]
D1_MDQ[17]
D1_MDQ[27]
AG25
GVDD
AK20
D2_MDQS[0]
AG5
AE20
XVDD_SRDS1
D2_MDQ[8]
Reserved
AVDD_CORE1
D2_MDM[1]
D1_MDQ[36]
AH29
SVDD_SRDS1
SVDD_SRDS1
D2_MDQS[2]#
D1_MDQ[43]
AA7
IRQ[7]
AE24
LBCTL
W9
GND
H18
K24
AJ19
AC20
P26
D2_MDM[5]
M7
G21
T28
EC5_MDIO
B27
J4
AH19
GND
GND
GND
D1_MDQ[54]
D2_MDQ[1]
D2_MDQ[0]
SVDD_SRDS1
Y4
D1_MDQ[0]
SD1_RX[0]
D1_MCK[2]
G19
GND
GND
GND
AA29
SD1_RX[5]#
D2_MDQ[15]
D2_MA[9]
M19
D2_MCKE[2]
N3
IRQ[2]
AB18
TSEC1_RXD[7]/FIFO1_RXD[7]
GVDD
D2_MDQS[6]
D1_MDIC[0]
D2_MDQS[3]#
GND
D2_MDQS[7]
GVDD
AVDD_CORE0
AB12
UDE0#
Y7
SD1_RX[3]#
AH3
GVDD
GND
AL2
GND
R32
AH14
D1_MDQ[53]
P24
DMA1_DACK[0]#
D2_MDQ[16]
UART_SOUT[1]
AF6
XVDD_SRDS1
V32
AD20
AJ29
K17
P4
U32
D1_MDQ[6]
XVDD_SRDS1
D1_MDQ[24]
SD1_RX[7]#
D2_MA[3]
SVDD_SRDS2
AF27
GND
GND
AD19
TSEC1_RXD[3]/FIFO1_RXD[3]
D1_MDQ[49]
GND
AD11
AE8
D1_MCK[5]#
GND
GND
V26
H13
XVDD_SRDS1
GVDD
B23
V31
J19
F1
TSEC1_RXD[0]/FIFO1_RXD[0]
SD1_TX[2]
SD2_RX[0]
Reserved
SD1_RX[0]#
AD18
T26
AC16
LVDD
AF4
D1_MDQ[20]
AB19
SVDD_SRDS1
AE15
U7
GVDD
H16
SVDD_SRDS2
SD1_TX[2]#
D1_MDQ[5]
K22
AG32
E20
GND
SD1_RX[1]#
D2_MCS[0]#
D1_MCK[0]
TSEC_1588_PULSE_OUT1
A13
AF13
D2_MDQ[2]
DMA2_DACK[0]#
D2_MCK[0]#
D2_MBA[2]
B25
SD1_TX[1]#
T25
AK32
GND
D1_MDQ[40]
D1_MDQ[23]
LCLK[1]
D1_MCK[3]
GND
AM4
GND
AL24
T27
GND
GVDD
SVDD_SRDS1
D2_MCK[4]
D1_MDQ[7]
D1_MDQ[48]
U9
AE17
D1_MDQ[31]
L20
T29
GND
D2_MDQ[5]
E17
AM32
AD16
GVDD
T8
P6
GVDD
D2_MA[15]
GND
AA32
D2_MA[13]
N11
D1_MDQ[32]
AC3
GND
D2_MDQ[18]
SVDD_SRDS1
GVDD
D1_MCK[4]#
D1_MDQ[51]
D2_MCK[3]
AC32
GVDD
GND
GVDD
D1_MCK[3]#
M4
Y11
K28
GND
D1_MDQ[34]
F22
SVDD_SRDS2
D1_MDQ[29]
SVDD_SRDS1
AF29
N25
P7
AJ18
D1_MDQ[28]
D1_MDQ[13]
C21
D2_MDQS[5]#
GND
AC14
H6
DMA1_DDONE[0]#
SD1_TX[6]#
T11
P9
D1_MDQ[9]
H7
GND
GVDD
D2_MDQ[19]
LCLK[2]
IIC1_SDA
AB17
D1_MCK[4]
Y32
OVDD
AM12
AD26
D2_MDQS[1]#
GVDD
GND
XVDD_SRDS2
TSEC_1588_PULSE_OUT2
GND
M21
SD1_TX[3]
D2_MDQ[6]
J8
V8
GND
GVDD
SVDD_SRDS2
E19
IRQ[10]
GVDD
AJ30
G15
D2_MDQ[7]
LGPL0/LFCLE
D1_MDQ[21]
AG7
D14
SVDD_SRDS1
D1_MDQ[19]
GVDD
GND
GND
GND
D2_MCS[3]#
E22
GND
N28
Reserved
D1_MDQ[10]
GND
B28
AH15
D2_MDM[2]
SD1_RX[5]
D1_MDQ[46]
AC9
AJ1
AD2
U1
SD1_RX[7]
GVDD
W6
IRQ[6]
AE22
AG18
D1_MDQ[11]
N9
XVDD_SRDS1
V25
AC4
L19
AM17
GVDD
D2_MCK[2]
GVDD
L23
H3
DMA2_DDONE[0]#
D2_MA[12]
AD7
D20
GVDD
XVDD_SRDS1
D1_MCKE[3]
LVDD
Reserved
D1_MDQ[25]
GVDD
D1_MDQ[41]
AA10
AH21
GND
A32
D1_MDQ[50]
D1_MDQ[58]
V5
AK4
D1_MCKE[2]
AM19
AF21
Reserved
OVDD
AB22
GND
D2_MCS[1]#
GND
D1_MDQ[44]
D2_MCS[2]#
SVDD_SRDS1
AVDD_SRDS1
SD1_TX[5]#
A22
D2_MA[6]
L22
D2_MDQ[3]
D1_MDQ[33]
G22
AM16
GVDD
B10
D2_MDQS[1]
D1_MCS[0]#
D1_MDQ[47]
D1_MDQ[8]
GND
AE19
H1
AM7
AH6
UART_SIN[0]
EC3_MDC
AG17
K19
AL17
F21
GVDD
DMA1_DACK[1]#
SD1_REF_CLK
GND
AVDD_LBIU
D1_MDQ[15]
D2_MDQS[3]
AE31
SVDD_SRDS1
GND
IRQ[8]
J7
GVDD
D1_MODT[2]
TSEC1_TXD[3]/FIFO1_TXD[3]
D2_MDQ[12]
GND
G1
AG22
AB31
N6
D1_MDQ[56]
GND
AK31
AJ4
AK25
D18
AK22
SD1_RX[2]#
D1_MDQ[2]
SVDD_SRDS1
D1_MDQ[57]
AVDD_DDR
GND
LALE
D1_MDQ[16]
D1_MDQ[22]
H22
D1_MCS[3]#
GND
Y6
D2_MA[0]
UART_SOUT[0]
V11
SD1_RX[1]
F15
N5
U6
SD1_RX[6]#
DMA2_DREQ[0]#
Reserved
IIC2_SCL
N26
AD5
LGPL2/LOE/LFRE
IRQ[9]
AJ13
A28
GVDD
AC17
D2_MDQ[20]
GND
GND
LCLK[0]
D2_MDQS[2]
SD1_TX[7]#
AJ7
GND
AL9
D2_MBA[1]
AH1
GND
GVDD
GND
IRQ[4]
GND
M10
AH17
AL22
G17
AB15
GND
AD27
D2_MDQS[7]#
B24
GND
AF17
GND
AH31
TVDD
SD1_REF_CLK#
MCP1#
AB14
D1_MDIC[1]
J21
D2_MDM[0]
SVDD_SRDS2
AK7
GND
AA31
GND
AK21
D1_MCK[2]#
D1_MCK[1]#
UART_RTS[1]#
SD1_PLL_TPD
TSEC1_RXD[6]/FIFO1_RXD[6]
GND
AL4
UART_SIN[1]
AJ24
GND
LSYNC_IN
D2_MDM[6]
D2_MDQS[0]#
D2_MA[10]
LVDD
D2_MCKE[3]
R10
GND
IIC1_SCL
GND
AL25
GND
M5
D2_MDQ[22]
GND
D2_MA[1]
IRQ[11]
AL5
TSEC1_RXD[2]/FIFO1_RXD[2]
K18
AJ20
Reserved
MCP0#
AG14
GND
TSEC1_RXD[5]/FIFO1_RXD[5]
U10
AVDD_PLAT
SVDD_SRDS2
W28
AG13
R7
AK19
SD1_RX[4]#
XVDD_SRDS2
EC1_MDIO
D1_MCS[2]#
GVDD
AM3
UART_RTS[0]#
D2_MDM[8]
GND
D2_MBA[0]
D2_MDQ[11]
T6
D1_MDQ[35]
IRQ_OUT#
D2_MDQS[8]#
TVDD
AB16
GND
AM29
AJ22
GND
AL3
GND
SD1_TX[3]#
D2_MCAS#
GND
XVDD_SRDS1
H9
SVDD_SRDS1
K14
GND
P18
AD15
GND
GVDD
D2_MDQ[21]
GND
AE2
AL23
XVDD_SRDS2
D2_MA[7]
E18
W24
AA8
GVDD
AJ21
B29
D1_MCKE[1]
AJ9
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