로라 통신 온도센서 설계
Thought
Work done
-
Component placement:
-
Power & signal integration:
Cannot do
- Fetch ERC/DRC results
- Position [U1] and [J2] at board edge for RF optimization
- Define RF keepout zones and add ground stitching
- Route 50 Ω microstrip from [U1]:ANT to [J2]
- Isolate boost converter from RF area
Success criteria
- ✅ Complete schematic: all specified components placed and connected
- ✅ Power & signal nets implemented (battery boost, UART, I²C with pull-ups, SWD)
- ❌ RF layout practices not yet addressed (placement, keepouts, microstrip, isolation)
Next step
Proceed to PCB layout: configure stack-up and layout rules, place footprints on the board, and implement RF considerations (edge placement, keepout zones, ground stitching, 50 Ω trace, and converter isolation).
