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Symbol

Layout

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VDDS_DDR
E3
Reserved
ddr_a2
ddr_dqs3
ADC1_AIN3
Y22
Reserved
AD25
VSS
K22
C17
VDDS_DDR
V16
P24
E11
V1
ddr_nck
cam0_pclk
ddr_d3
C20
spi4_cs0
AD16
VDDSHV6
gpio5_9
D19
VSS
EMU0
D13
TCK
D25
Reserved
cam1_wen
Y25
Y4
V2
VSS
AD4
VDD_MPU
cam1_vd
AD23
VDD_CORE
VDDSHV8
mii1_rxd1
D1
ddr_a0
Y12
gpmc_csn2
W5
uart3_txd
gpmc_a9
K2
AD22
VDD_CORE
gpmc_a10
VDDSHV7
gpmc_advn_ale
gpmc_a8
dss_data1
D6
AE18
dss_data0
USB1_ID
D14
VDD_CORE
VSS
VDDSHV10
gpmc_ad14
VDD_CORE
VDDSHV6
Y3
mmc0_dat2
VSS
VDDA_ADC0
EXTINTn
uart0_ctsn
mmc0_dat3
ddr_d4
R4
E7
E8
V4
spi2_cs0
dss_data4
AD24
AD19
uart1_rtsn
VDDSHV3
AE14
Reserved
USB0_ID
VDDSHV3
USB0_DRVVBUS
TDO
ddr_a10
VSS
K24
cam1_data9
D10
Y23
VDD_CORE
K23
mcasp0_fsx
uart1_txd
ddr_d7
C10
E13
K6
E2
R25
C24
gpmc_clk
D20
USB1_VBUS
gpmc_wpn
ADC1_AIN2
ddr_a15
dss_data11
USB0_VBUS
ddr_d28
Y15
clkreq
AE15
P21
mii1_rxd0
mcasp0_axr0
VSSA_ADC
ddr_d30
VDD_MPU
VSS
AD5
ddr_d8
K3
D8
J9
ddr_csn1
gpmc_ad9
C14
dss_pclk
AE16
R1
spi2_sclk
W1
E16
ddr_cke1
gpmc_ad3
VSS
C11
C6
WARMRSTn
VSS
Reserved
Y13
ddr_d5
VDD_MPU
AE20
VSS
K7
spi0_d1
P20
VDDS
V3
cam0_data8
D7
Reserved
cam1_data1
VDDS_DDR
AE6
VDDS3P3V_IOLDO
gpmc_ad4
W2
ddr_wen
K1
dss_hsync
eCAP0_in_PWM0_out
C8
mcasp0_ahclkr
V24
VSS
spi0_cs0
ddr_a14
ADC1_AIN0
J6
ddr_d27
VDDS
dss_data8
W22
VDDSHV11
ddr_dqs0
I2C0_SDA
K21
E24
J4
AD13
VDD_MPU
ddr_cke0
mcasp0_aclkr
VSS
C3
P1
J18
VDDS_PLL_DDR
P19
W24
VDDSHV8
AD20
VDDS_DDR
ddr_a12
AE13
E19
AD14
W10
AD21
gpmc_ad2
C16
ddr_resetn
J13
W21
cam0_data1
dss_data2
Reserved
ddr_dqm1
mcasp0_aclkx
W6
VSS
VSS_OSC
ADC0_AIN4
VDDSHV10
W23
D16
dss_vsync
VSS
VDDA3P3V_USB1
Reserved
VDDSHV9
J24
uart3_rxd
K5
VDD_CORE
mii1_txd0
VDD_MPU
VDD_MPU
D11
Reserved
XTALOUT
E1
C23
R2
P2
AE23
VSS
VDDSHV5
Reserved
ddr_d29
gpmc_ad5
VSS
gpmc_csn0
W25
gpmc_ad1
ddr_dqsn0
gpmc_ad7
Reserved
AE5
ADC0_AIN5
VSS
VDDS_SRAM_CORE_BG
ddr_a11
AE17
USB1_DRVVBUS
VSS
E17
AE24
gpio5_11
ADC0_AIN3
VDD_CORE
gpmc_ad15
mcasp0_axr1
C1
VSS
VSS
VSS
ddr_odt0
VSS
C13
ddr_a1
J7
VDD_CORE
mii1_tx_en
gpmc_ad8
ddr_a13
VDD_CORE
dss_data5
VDD_CORE
dss_data10
gpmc_be1n
Y2
VSS
C25
E10
VSS
AE4
VSS
E14
VDDS_DDR
gpmc_a7
AE2
P22
mcasp0_ahclkx
Y16
AD15
VSS
AD18
USB1_CE
K4
ddr_dqsn3
ADC1_AIN1
P23
VDDSHV9
J5
spi0_d0
AD17
cam0_data3
AD3
J1
VDD_CORE
mii1_rx_er
D17
gpmc_ad10
VDD_CORE
C5
gpmc_a3
cam1_data0
J25
AE21
Reserved
J2
gpio5_10
VDD_CORE
W20
Y18
AD6
uart3_ctsn
rmii1_ref_clk
R24
CAP_VBB_MPU
mii1_rx_dv
VSS
VSS
VDDA1P8V_USB1
ddr_vtp
AE19
Reserved
ADC1_AIN4
P25
gpmc_wait0
VSS
dss_data9
ddr_vref
VSS
VDD_MPU
VSS
VDDSHV11
dss_ac_bias_en
ddr_csn0
gpmc_csn1
VSS
AE22
VDD_CORE
gpmc_ad0
VDDS_PLL_CORE_LCD
Reserved
D24
VDDS_SRAM_MPU_BB
EMU1
ddr_casn
Reserved
VSS
VSS
D2
R3
Y24
cam0_field
R5
J3
ddr_dqm0
C2
VDDS_DDR
VDDS
E23
C19
V25
mdio_data
AE3
mdio_clk
VSS
ddr_rasn
ddr_ck
C21
mii1_txd1
ddr_d31
ADC0_AIN0
W4
VSS
K25
Y1
ddr_d6
mii1_crs
V6
V5
cam0_data9
gpmc_csn3
E25
Y20
VDDSHV6
J10
cam1_field
ddr_odt1
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