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VDD_CORE
VSS
VSS
VSS
dss_ac_bias_en
AC15
TMS
mcasp0_fsr
USB1_VBUS
RTC_PWRONRSTn
gpmc_a11
VDD_MPU
uart0_rtsn
Reserved
dss_data12
mdio_clk
VDD_CORE
uart3_ctsn
VSS
ddr_d8
RTC_XTALIN
mii1_crs
ddr_a7
ddr_d16
VDD_CORE
ddr_csn1
VSS
VDD_MPU
dss_hsync
VDD_CORE
ddr_dqsn0
mdio_data
Reserved
gpmc_ad10
USB0_CE
VSS
ddr_a1
ddr_cke0
K7
ddr_d14
ddr_ck
gpmc_ad14
XTALIN
spi4_d0
mii1_rxd3
XTALOUT
mmc0_dat1
VSS
uart1_rxd
U20
dss_data8
gpmc_oen_ren
ADC1_VREFP
ddr_dqsn2
gpmc_be1n
VSS
Reserved
gpmc_ad8
VDD_MPU
ddr_dqm2
Reserved
dss_data1
spi0_sclk
mii1_rx_er
CAP_VDDS1P8V_IOLDO
ddr_a14
ddr_d24
xdma_event_intr0
Reserved
VDD_CORE
uart0_rxd
CAP_VDD_RTC
mii1_txd1
ADC1_AIN2
cam1_pclk
ddr_d13
VSS
ddr_d30
W20
EMU1
spi4_d1
cam0_data3
Reserved
G11
ADC0_AIN0
B24
G10
VDD_CORE
CAP_VBB_MPU
VSS
ADC1_AIN0
ddr_dqs3
USB0_VBUS
mmc0_dat0
gpmc_csn1
uart0_ctsn
gpmc_ad9
ddr_vref
spi4_cs0
mii1_tx_en
gpmc_be0n_cle
ddr_a15
Reserved
cam0_data9
USB1_DM
cam1_data5
gpio5_10
ddr_a5
uart3_rtsn
VSS
ddr_d29
spi0_d0
gpmc_ad4
ddr_a12
cam1_wen
mii1_txd3
Reserved
ddr_d7
Y16
H8
ADC0_AIN1
VSS
Reserved
ddr_a0
CAP_VDD_SRAM_MPU
spi2_sclk
uart1_rtsn
ddr_a8
gpmc_a9
ddr_d0
gpmc_wait0
cam1_data1
ddr_d9
Reserved
mcasp0_fsx
gpmc_ad2
ddr_d12
F13
gpmc_ad7
EMU0
RTC_PMIC_EN
USB1_CE
E17
ddr_d4
VDD_CORE
VDD_CORE
VSS
G13
eCAP0_in_PWM0_out
ddr_d15
ddr_d5
spi0_cs0
F8
Reserved
ddr_dqm1
ddr_wen
USB0_DP
dss_data13
clkreq
dss_data14
gpmc_ad3
W21
gpmc_ad5
ddr_dqm0
spi0_cs1
ddr_d25
cam0_data0
VDD_MPU
ADC1_VREFN
Reserved
dss_pclk
Reserved
Reserved
ADC0_VREFP
cam1_data8
U21
G5
ddr_odt0
dss_data3
Reserved
spi2_d1
WARMRSTn
cam0_field
CAP_VDD_SRAM_CORE
V16
cam0_hd
VSS
ddr_a11
xdma_event_intr1
dss_data4
VSS
Reserved
ddr_dqs2
cam0_data5
rmii1_ref_clk
VSS
AD4
ddr_d27
VDD_CORE
ddr_dqsn1
VSS
VDD_CORE
RTC_KALDO_ENn
VSS
VSS
ddr_a9
VSS
USB1_ID
mcasp0_ahclkx
gpmc_a3
dss_data9
ddr_d10
Reserved
VSS
TDI
I2C0_SCL
mcasp0_axr0
VDD_CORE
AB12
Reserved
ddr_csn0
ddr_d21
VDD_CORE
P21
Reserved
VSS
F20
ddr_dqs0
gpmc_advn_ale
ddr_cke1
gpmc_ad15
VDD_CORE
ddr_ba0
VDD_MPU
ddr_d31
P15
RTC_WAKEUP
dss_data2
spi4_sclk
mii1_txd0
ADC0_AIN6
USB0_DM
cam0_pclk
dss_data15
spi2_d0
TDO
ddr_dqsn3
VSS
VDD_CORE
ddr_d19
cam1_data7
cam1_data3
AD5
ddr_d28
ddr_a4
cam1_hd
mmc0_cmd
ddr_d20
ddr_nck
VSS
ADC1_AIN1
VDD_MPU
gpmc_a10
ddr_a6
ddr_d22
gpmc_a4
cam1_data0
cam1_data6
E23
VDD_MPU
ADC1_AIN6
Reserved
Reserved
J18
VSS
mii1_rx_clk
dss_data7
dss_data0
USB1_DRVVBUS
Reserved
F14
ADC0_AIN5
ADC1_AIN7
VDD_CORE
mii1_rxd0
VDD_CORE
VSS
TCK
cam0_data8
gpmc_csn2
ADC0_AIN7
VSS
ddr_d18
mii1_col
mcasp0_axr1
ADC0_AIN4
spi2_cs0
gpio5_12
gpmc_ad1
gpmc_ad11
ddr_d26
VDD_MPU
VSS
cam1_vd
VDD_CORE
USB0_DRVVBUS
VDD_CORE
ddr_d6
mmc0_clk
dss_data11
nTRST
I2C0_SDA
Reserved
VDD_CORE
ddr_d17
mii1_tx_clk
ddr_dqs1
VDD_MPU
cam0_data7
gpmc_ad0
gpio5_8
ADC1_AIN5
cam1_data4
uart1_ctsn
gpmc_ad13
RTC_XTALOUT
Reserved
N21
gpmc_a0
gpmc_a6
uart3_txd
gpmc_csn3
EXTINTn
VSS
ddr_ba2
gpmc_csn0
ddr_a2
gpmc_wpn
VDD_MPU
ddr_dqm3
VSS
F16
cam0_data4
dss_data10
VDD_CORE
gpmc_a1
VDD_CORE
VSS
gpmc_ad6
Reserved
gpmc_a8
uart0_txd
VDD_CORE
mmc0_dat3
ddr_resetn
VDD_CORE
ADC1_AIN4
PWRONRSTn
gpio5_13
ddr_d3
spi0_d1
mii1_rx_dv
gpmc_clk
VDD_MPU
uart3_rxd
ddr_d23
mii1_txd2
mcasp0_aclkr
mcasp0_aclkx
ADC0_VREFN
cam1_data2
USB1_DP
dss_data6
ddr_a10
gpmc_ad12
ddr_rasn
cam0_vd
dss_vsync
ADC0_AIN3
VSS
gpmc_wen
F22
VSS
cam0_data6
gpmc_a2
ddr_casn
VDD_CORE
ddr_vtp
ADC0_AIN2
ddr_a3
Reserved
ADC1_AIN3
VSS
USB0_ID
VSS
cam0_data2
G16
cam0_data1
dss_data5
VSS
VSS
ddr_d11
D20
ddr_ba1
mii1_rxd1
cam0_wen
VDD_MPU
ddr_a13
gpmc_a7
cam1_data9
gpio5_11
mcasp0_ahclkr
C23
uart1_txd
ddr_d1
Reserved
J7
mii1_rxd2
mmc0_dat2
VDD_CORE
gpmc_a5
ddr_d2
cam1_field
W23
ddr_odt1
gpio5_9
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Assets
kicad_mod
AM4372BZDN60/AM4372BZDN60.pretty/BGA-491_L17.0-W17.0-P0.65-BR_TI_ZDN.kicad_mod
AM4372BZDN60/AM4372BZDN60 FootprintFootprint
AM4372BZDN60 AM4372BZDN60_1_1 Symbol.svg
AM4372BZDN60 AM4372BZDN60_1_1 SymbolDefaultAM4372BZDN60
Microcontroller Units (MCUs/MPUs/SOCs)
AM4372BZDN60
BGA-491_L17.0-W17.0-P0.65-BR_TI_ZDN
LCSC Part Number: C1555572
JLCPCB Part Class: Extended Part
Manufactured by TI(德州仪器)
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