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A4
VDDD
TCK
TCLK1
RTIP1
D4
TDI
TCLK2
A1
GNDT1
SDO
VDDR1
RCLK1
A2
TTIP2
TDN2
VDDT1
RD3/RDP3
VDDIO
TD1/TDP1
RCLK4
NC
A7
NC
VDDIO
IC
RRING4
TMS
~{TRST}
A0
GNDR3
RCLK2
TCLK4
NC
GNDT4
LOS3
VDDT4
VDDT1
GNDIO
RTIP3
GNDT3
GNDT3
GNDT1
INT/~{MOT}
VDDR3
REF
GNDT4
TTIP3
LOS1
GNDD
P/~{S}
RTIP2
TD4/TDP4
TDN4
GNDR4
VDDT2
THZ
IC
RRING2
VDDA
VDDA
A3
GNDA
VDDIO
VDDD
CV4/RDN4
~{DS}/~{RD}
TRING2
A5
~{INT}
D6
TD2/TDP2
SDI/R/~{W}/~{WR}
MCLKS
VDDT2
~{RST}
GNDT2
D1
RRING1
TCLK3
GNDIO
MCLK
LOS4
RD4/RDP4
VDDIO
D3
VDDT3
VDDT3
D7
VDDT4
TRING3
RRING3
CV3/RDN3
SCLKE
D0
GNDR2
~{CS}
RCLK3
SCLK
GNDIO
RTIP4
GNDA
TDN3
CV2/RDN2
D2
LOS2
TTIP1
VDDR2
TDO
GNDR1
TRING1
VDDIO
VDDR4
CV1/RDN1
TRING4
NC
RD1/RDP1
A6
RD2/RDP2
GNDT2
GNDIO
TTIP4
GNDIO
IC
TDN1
GNDD
TD3/TDP3
D5
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