2N7002 Datasheet Guide


I’ll research the MDD 2N7002 datasheet, verify replacement options and sourcing details, and write a cited application guide in the project files.
The attached MDD datasheet conflicts with the catalog description on current, power dissipation, and on-resistance. I’ll make that discrepancy explicit and distinguish pin-compatible alternatives from electrically interchangeable replacements.
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2N7002 Application and Usage Guide

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2N7002 Application and Usage Guide
The MDD 2N7002 is an enhancement-mode N-channel MOSFET in a three-terminal SOT-23 package, with a 60 V absolute maximum drain-source rating. A practical use is a low-side small-load switch controlled by a GPIO or gate driver; the source connects to ground and the drain connects to the load return, following the low-side topology described in TI's MOSFET design guide.
Scope and verification warning: This guide applies specifically to the MDD datasheet attached to this Flux part, version V 1.0, not to every manufacturer's 2N7002. The project descript...
Created the cited 2N7002 Application and Usage Guide in the project files, covering all seven requested sections. It flags conflicting catalog and datasheet ratings, qualifies replacement compatibility, and identifies sourcing details that could not be verified; confirm the datasheet for the actual supplier stock before production use.

2N7002 Application and Usage Guide
The MDD 2N7002 is an enhancement-mode N-channel MOSFET in a three-terminal SOT-23 package, with a 60 V absolute maximum drain-source rating. A practical use is a low-side small-load switch controlled by a GPIO or gate driver; the source connects to ground and the drain connects to the load return, following the low-side topology described in TI's MOSFET design guide.
Scope and verification warning: This guide applies specifically to the MDD datasheet attached to this Flux part, version V 1.0, not to every manufacturer's 2N7002. The project description says 115 mA, 200 mW, and 1.7 Ω at 5 V/50 mA, while the attached MDD datasheet specifies 340 mA, 350 mW, and different on-resistance conditions. The project also has a separate 200 mA current property. These catalog values are inconsistent; the table below reproduces the attached datasheet, but its applicability to actual C472906 stock must be confirmed with MDD/LCSC before production release. No catalog properties, symbol, or footprint were changed.
1. Quick Specifications
Absolute maximum ratings are stress limits, not recommended continuous operating targets. Electrical-characteristic test conditions do not establish a universal recommended operating range.

Table


ParameterValue and conditionsClassification
Drain-source voltage, VDS60 VAbsolute maximum; TA = 25 °C unless otherwise noted.
Gate-source voltage, VGS±20 VAbsolute maximum.
Continuous drain current, ID340 mAAbsolute maximum in the attached MDD sheet, not an unconditional usable load current.
Pulsed drain current, IDM1.5 AAbsolute maximum; pulse width limited by maximum allowable junction temperature.
Power dissipation, PD350 mWAbsolute maximum under the datasheet's board conditions.
Junction/storage temperature, TJ/Tstg−50 to +150 °CAbsolute maximum range; not an ambient-temperature recommendation.
Junction-to-ambient thermal resistance, RθJA357 °C/WBoard-dependent thermal characterization.
RDS(on), VGS = 10 V, ID = 300 mA1.2 Ω typical; 2.5 Ω maximumElectrical characteristic at the stated test conditions.
RDS(on), VGS = 4.5 V, ID = 200 mA1.3 Ω typical; 3.0 Ω maximumElectrical characteristic; no verified maximum at 3.3 V in this guide.
Gate threshold, VGS(th)1.0 V minimum, 1.5 V typical, 2.5 V maximum; VDS = VGS, ID = 250 µATurn-on threshold measurement, not full-enhancement voltage.
Package and terminal spacingSOT-23; body length D = 2.8–3.1 mm, typical 2.9 mm; e = 1.8–2.0 mm, typical 1.9 mm between the two same-side terminalsMechanical dimensions; do not confuse this spacing with adjacent staggered-pad spacing.
Recommended operating conditionsNo numerical recommended-operating-conditions table was found in the attached five-page sheetNot verified as a manufacturer-recommended range.
The PD and RθJA figures were measured on a 1 in² double-sided FR-4 board with 2 oz copper in still air at TA = 25 °C; a small footprint on a different PCB may have different thermal performance.
Practical operating recommendation, not a datasheet rating: Use a gate-drive level corresponding to a verified RDS(on) test point, leave voltage and temperature margin, and check conduction plus switching losses at the actual load. A 3.3 V GPIO may switch a light load, but do not claim guaranteed low resistance from VGS(th); select a MOSFET with an explicit low-voltage RDS(on) guarantee when that guarantee is required. See TI, sections 4–6.
2. Pinout & Connections
Pin assignments follow the MDD SOT-23 package drawing. The recommendations below are for a low-side switch, not a level-shifter or high-side circuit.

Table


Pin NumberPin NameDescriptionBest Practice
1G — GateInsulated control terminal. Drive relative to Source. Add a 100 kΩ gate-to-source pull-down as a starting design choice to keep the switch off during GPIO reset/high impedance; never leave the gate floating.
2S — SourceLow-side current-return terminal. Tie to GND for this topology; share ground with the controller and keep the gate-drive return short.
3D — DrainSwitched load-return node. Connect to the load's negative terminal; connect the load's positive terminal to its supply. Provide a clamp for an inductive load.
Check physical pad numbers against the package drawing rather than trusting the symbol's appearance. A gate-to-source resistor prevents charge accumulation when the drive is disconnected; TI discusses a 10 kΩ–1 MΩ range, with the appropriate value depending on leakage and noise requirements (TI, section 6).
3. Standard Application Circuit
GPIO-controlled 2N7002 low-side switch

Text


+VLOAD ── LOAD ── D (pin 3)
                  2N7002
GND ──────────── S (pin 2)

GPIO ── RG ───── G (pin 1)
                 │
              100 kΩ
                 │
               S / GND
  • Pull-down: Start with 100 kΩ from Gate to Source. This is an engineering starting value, not an MDD-required component value. Use a lower resistance if leakage, cable coupling, or fast drain transitions compromise the off state; verify the driver's ability to supply the additional DC current.
  • Series gate resistor RG: For a slow GPIO-controlled switch, 100 Ω is a reasonable initial damping value, not a universal requirement. Increase it if needed to meet the GPIO peak-current limit; estimate initial current as Ipeak ≈ VGPIO/(RG + driver output resistance), then check the controller datasheet and switching waveform. A larger resistor reduces gate current but increases switching time and potentially switching loss. See TI External Gate Resistor Selection Guide.
  • Gate drive: Use a drive level consistent with the published on-resistance conditions. The MDD maximum RDS(on) is 3.0 Ω at VGS = 4.5 V/ID = 200 mA and 2.5 Ω at VGS = 10 V/ID = 300 mA. Check the actual driver's minimum VOH, not just its nominal supply voltage.
  • Inductive load: Add a flyback diode across a relay coil or other inductive load: cathode to +VLOAD, anode to Drain. Choose reverse-voltage and forward/pulse-current ratings for the actual supply and coil current. Do not rely on unspecified repetitive avalanche capability. A diode clamp slows coil release; use an appropriately rated higher-voltage clamp if fast release is required. The broader need to limit turn-off voltage from stored inductive energy is explained in TI's snubber discussion.
  • Decoupling: The MOSFET has no supply pin and does not require an IN-pin decoupling capacitor. Put load-supply decoupling/bulk capacitance near the switching-current loop as required by the load and wiring; capacitance is load-dependent, so no universal 1 µF requirement is claimed.
  • LED load: If the load is an LED, it still needs a series resistor: RLED = (VLOAD − VF − VDS(on))/ILED. The GPIO controls the gate and does not set LED current directly. No fixed 3.3 V/5 V resistor values can be specified without the LED's VF and target current.
Loss check: Use Pcond ≈ I²RDS(on)D, where D is duty cycle, and add switching losses. As an illustrative calculation at the MDD 4.5 V test point, continuous 200 mA and 3.0 Ω gives 0.12 W conduction loss and 0.60 V drop; using the stated 357 °C/W gives about 43 °C rise on the datasheet test board. These are calculated estimates using 25 °C resistance and the datasheet board conditions, not a hot-junction guarantee; resistance and board thermal behavior must be assessed at operating temperature.
4. PCB Layout & Routing Guidelines
  • Confirm the SOT-23 land pattern and pad mapping. Use the MDD outline rather than a package-name assumption; its typical body length is 2.9 mm and its same-side terminal spacing is 1.9 mm. The actual Flux footprint was not geometrically audited in this documentation task.
  • Keep the gate-drive loop compact. Place RG near the Gate and the pull-down close to Gate/Source; route the controller's ground reference back to Source without sharing a long load-current return. Short loops reduce parasitic inductance; see TI gate-resistor guidance.
  • Size Drain/Source copper for load current and heat. Select trace width from copper thickness, allowable voltage drop, and temperature rise rather than assigning a universal width. Extra copper helps spread heat; narrow thermal-relief spokes can restrict that path, so balance reflow solderability against thermal performance. The 357 °C/W figure is tied to the datasheet's specific test board, not every layout.
  • Minimize the switched-load loop. Keep an inductive-load clamp near the load connection/switching loop, and keep the Drain node away from high-impedance analog inputs and the Gate trace. Locate load-rail decoupling to support local current changes, not at the gate.
  • No differential-pair rules apply. Gate, Drain, and Source are not a differential interface; do not apply USB-style impedance or pair-length rules. Follow the actual PCB fabricator's solder-mask, pad-clearance, and assembly constraints.
5. Common Pitfalls / Things to Watch Out For
  1. Treating threshold voltage as full enhancement—or leaving Gate floating. VGS(th) is measured at only 250 µA, whereas the on-resistance specifications use much higher drive voltages and currents. Use a gate-to-source pull-down and verify performance at the driver's worst-case VOH; TI's guide explains both failure mechanisms.
  2. Treating “2N7002” or ID(max) as a universal guarantee. Different manufacturers use different dies, resistance limits, and thermal conditions. This part's catalog metadata already conflicts with its attached sheet. Check actual lot documentation, dissipation, temperature, and inductive turn-off voltage before accepting a substitution or running near a stress limit.
These are conditional replacement candidates, not unconditional electrical drop-ins. The cited sheets verify the same Gate/Source/Drain numbering and SOT-23 package class; the actual PCB land pattern, clearance, thermal design, switching behavior, and assembly library still require comparison.

Table


AlternativeCompatibilityVerified comparison and qualification action
Nexperia 2N7002BK,215 in FluxPin-compatible: 1 G, 2 S, 3 D; SOT-23 footprint-class compatible, exact land-pattern fit not audited. Attached library datasheet gives RDS(on) 1 Ω typical/1.6 Ω maximum at VGS = 10 V, ID = 500 mA, TJ = 25 °C. Recheck ratings, low-voltage gate drive, capacitance, and timing for the application. The newer manufacturer-hosted sheet lookup remained unresolved; this comparison uses the successfully verified library-attached sheet.
onsemi 2N7002LT1GPin-compatible: 1 G, 2 S, 3 D; SOT-23 Case 318 Style 21, footprint-class compatible but exact fit not audited. Maximum RDS(on) is 7.5 Ω at 10 V/500 mA and 5 V/50 mA at TC = 25 °C; continuous-current maximum is 115 mA at TC = 25 °C. Not suitable as an automatic replacement for a design relying on the MDD 340 mA or lower resistance. No exact LT1G library match was confirmed; do not substitute the similarly named KT1G or LRC L2N7002LT1G without a separate review.
Library presence is not proof of live distributor stock or fabrication readiness. Do not substitute SOT-323 “W” variants or dual-MOSFET packages onto a SOT-23 footprint based on the shared family name.
7. Sourcing & Purchasing Guide

Table


AttributeDetails
Primary DistributorsThe project identifies the MDD device as LCSC C472906. Both the legacy LCSC listing and short listing URL returned “page not found” during this research. Current availability and authorized-channel status for this exact SKU are therefore unverified. For alternatives, use manufacturer-directed distributors such as DigiKey or Mouser after checking authorization for the selected manufacturer; do not imply that they stock this exact MDD part.
Packaging OptionsMDD C472906 tape/reel and cut-tape options are unverified. A different MDD 2N7002K document is not evidence for this 2N7002. For comparison only, onsemi LT1G is explicitly SOT-23 Pb-Free, 3,000 Tape & Reel.
Standard MOQExact MDD/LCSC MOQ and full-reel quantity could not be verified. Do not assume 1-unit cut tape or 3,000-unit reels. The onsemi LT1G 3,000-piece reel quantity is packaging information, not a universal distributor MOQ.
Sourcing AdviceObtain a current supplier quote and manufacturer-confirmed datasheet for the actual orderable code/lot. Confirm manufacturer, SOT-23 pin mapping, ordering suffix, packaging quantity, and electrical limits. Prefer manufacturer-authorized/franchised channels with traceability and avoid unverifiable marketplace stock. Recheck JLCPCB assembly availability/class at order time; the saved “Extended Part” tag is not a live availability check.
Sources
  • MDD 2N7002 manufacturer-authored datasheet, V 1.0, five pages, attached to this part: 2407101108_MDD-Microdiode-Semiconductor-2N7002_C472906.pdf. Manufacturer website printed in the document: www.microdiode.com; publication/revision date not stated. The hosting filename date is not treated as a document revision date.
  • Nexperia 2N7002BK library-attached manufacturer datasheet: 2304140030_Nexperia-2N7002BK-215_C282405.pdf. Revision/date not extracted. The current manufacturer-hosted PDF was located, but its evidence extraction remained pending after retry; newer-revision specifications were not used as verified evidence.
  • onsemi 2N7002L/2V7002L, 2N7002L/D: manufacturer PDF. Search indexed June 2024, Rev. 11; that revision/date was not separately citation-verified, while the pinout, resistance, current, and LT1G packaging claims above were verified from the PDF.
  • Texas Instruments, Avoid Common Mistakes When Selecting and Designing With Power MOSFETs, SLPA021: application report, especially sections 4–6 on gate voltage, low-side drive, and gate-to-source resistors. Revision/date not independently verified.
  • Texas Instruments, External Gate Resistor Selection Guide, SLLA385A: application brief, Rev. A as identified by the indexed title; publication date not verified.
  • Texas Instruments, Snubbing the Flyback Converter: technical article, used for the general inductive turn-off/clamping principle, not as a specific 2N7002 relay circuit reference; publication date not verified.
  • LCSC C472906 product listing: links in section 7, unavailable during research. Project identifiers and saved catalog values were read directly from the current Flux project, not treated as manufacturer guarantees.
Research checked 2026-10-06. Component-specific numeric claims use validated inline datasheet evidence; design starting values and calculated examples are explicitly identified as engineering recommendations or derivations.
  • 1. Quick Specifications

  • 2. Pinout & Connections

  • 3. Standard Application Circuit

  • GPIO-controlled 2N7002 low-side switch

  • 4. PCB Layout & Routing Guidelines

  • 5. Common Pitfalls / Things to Watch Out For

  • 6. Popular Alternatives & Equivalents

  • 7. Sourcing & Purchasing Guide

  • Sources