I2C and 1-Wire Connection Setup
1:22
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#Goal
- Redraw the entire DS28E18-based 1-Wire to I2C node as specified: Place the I2C group with a 4-pin 2.54 mm THT header (J3) on the left with pin mapping: Pin1=3V3, Pin2=GND, Pin3=SDA, Pin4=SCL; position the DS28E18 adjacent to the header; and place the trunk connectors on the right using Phoenix Contact 1712805 (J1/J2) with the pin mapping: Pin1=TRUNK_VPLUS, Pin2=TRUNK_DQ, Pin3=GND, Pin4=NC. Maintain pass-through for VPLUS and DQ between J2 and J1. Integrate a 33 Ω series resistor on DQ with a TVS diode (PESD5V0S1BBN) to GND, add 4.7k I2C pull-ups to 3V3, and include test pads for DQ, 3V3, and GND. Ensure a clean schematic redraw by cleaning up net duplicates and validating ERC/DRC.
#Implementation plan
1. Normalize connectors and nets
1. Reconfigure J1 and J2 using Phoenix Contact 1712805 with the specified pin mapping: Pin1=TRUNK_VPLUS, Pin2=TRUNK_DQ, Pin3=GND, and Pin4=NC.
2. Update the 4-pin THT header (J3) with a 2.54 mm pitch and pin assignments: Pin1=3V3, Pin2=GND, Pin3=SDA, Pin4=SCL.
2. Rewire 1-Wire and I2C paths
1. Connect the DS28E18 so its IO pin connects through a 33 Ω resistor (R1) to the DQ protection net (DQ_PROTECTED), then branch to D1 (TVS diode) tied to GND.
2. Maintain the pass-through connection for VPLUS and DQ between J2 and J1.
3. Connect the DS28E18 power and ground appropriately, ensuring its VDD is supplied and connected to the 3V3 net when needed.
3. Implement and configure I2C group
1. Connect the I2C signals from DS28E18 to the THT header J3 where Pin3 and Pin4 are SDA and SCL respectively.
2. Place 4.7k pull-up resistors (R2 and R3) from SDA and SCL to 3V3 to meet I2C bus requirements.
4. Add test pads and finalize foundations
1. Add test pads for monitoring DQ_PROTECTED, 3V3, and GND nets.
2. Clean up net portals, remove duplicates, and reconnect all nets ensuring proper naming (TRUNK_VPLUS, TRUNK_DQ, DQ_PROTECTED, 3V3, GND, I2C_SDA, and I2C_SCL).
5. Validate design
1. Run ERC/DRC to verify proper connectivity and absence of errors.
2. Update the project description to reflect the left/right placement of the connectors and overall architecture.
#Success criteria
- The schematic is redrawn meeting the specified architecture with all connectors and components correctly placed and connected.
- DQ protection with a 33 Ω resistor and TVS diode, I2C pull-ups and pass-through connections are implemented as specified.
- ERC/DRC passes with no errors and the test pads for DQ, 3V3, and GND are correctly placed.
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1:05
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added required connectors, bridge, passives, testpads
0:31
Started: adding DS28E18, connectors, passives, testpads
Using Schematic Tool.
Added 11 components
0:02
Added 2x 1712805 as J1, J2
Added 1x 215297-4 as J3
Added 1x DS28E18Q+T as IC1
Added 1x PESD5V0S1BBN as D1
Added 3x Generic Resistor as R1, R2, R3
Added 3x Generic Non-Plated Mounting Hole as Hole1, Hole2, Hole3
Execution stopped due to insufficient credits.
0:02
Using Schematic Tool.
Started: inspecting pins and wiring all nets
Ready.
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Distributor | Qty 1 |
|---|---|
Arrow | $23.53–$41.96 |
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