Part Data Analysis and Verification
19:54
Analyzing the schematic.
Analyzing the PCB layout.
Looking for "Absolute Maximum Ratings table values and notes" in dp83867e
Looking for "Recommended Operating Conditions table values" in dp83867e
Looking for "Electrical Characteristics table supply currents and voltages" in dp83867e
Looking for "Pin functions pin description table" in dp83867e
Looking for "Package dimensions drawing RGZ0048B" in dp83867e
Looking for "Features list and special functions SGMII RGMII" in dp83867e
Retry.
Looking for "Absolute Maximum Ratings" in dp83867e
Looking for "Recommended Operating Conditions" in dp83867e
Looking for "Pin functions" in dp83867e
Running multiple web searches.
Found 1 results.
Found 1 results.
Looking for "Absolute maximum ratings table: list each parameter and value" in dp83867e.pdf
Looking for "Recommended operating conditions table: supply voltages and temperature range" in dp83867e.pdf
Looking for "Electrical characteristics: supply current numbers and IO voltage ranges" in dp83867e.pdf
Looking for "Pin functions table for RGZ 48: pin number, name, type, description" in dp83867e.pdf
Looking for "Package information: RGZ0048B mechanical dimensions and land pattern" in dp83867e.pdf
Looking for "Features: interface modes RGMII SGMII 1000BASE-T 100BASE-TX and special features" in dp83867e.pdf
Looking for "ABSOLUTE MAXIMUM RATINGS" in dp83867e.pdf
Looking for "RECOMMENDED OPERATING CONDITIONS" in dp83867e.pdf
Looking for "Terminal Functions" in dp83867e.pdf
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Looking for "RGZ0048B" in dp83867e.pdf
Looking for "Terminal Functions table 7-? pin descriptions RGZ" in dp83867e.pdf
Looking for "7.3 Terminal Functions" in dp83867e.pdf
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Looking for "Table 5-1. Pin Functions pin 14 15 16 17 18 19" in dp83867e.pdf
Looking for "Table 5-1. Pin Functions MDIO MDC RESET INT_PWDN JTAG" in dp83867e.pdf
Looking for "Table 5-1. Pin Functions GPIO_0 GPIO_1 CLK_OUT X_I X_O" in dp83867e.pdf
Looking for "6.5 Electrical Characteristics supply current VDDA2P5 VDDA1P8 VDD1P0" in dp83867e.pdf
Looking for "Power consumption current typical 1000BASE-T" in dp83867e.pdf
Looking for "VDDIO input thresholds and output levels" in dp83867e.pdf
Looking for "6.5 Electrical Characteristics" in dp83867e.pdf
Craft.
1) Available part information (from this part project)
| Field | Value |
|---|---|
| MPN | DP83867ERGZR |
| Manufacturer | Texas Instruments |
| Package / footprint family (project description) | RGZ0048B (VQFN) |
| Pin count (from symbol/footprint in this project) | 49 terminals (pins 1-48 + exposed pad 49) |
| Datasheet URL (already set on the project) | https://www.ti.com/lit/gpn/dp83867e |
- Supply voltage:
- VDDA2P5: -0.3 V to 3 V
- VDDA1P8: -0.3 V to 2.1 V
- VDD1P0: -0.3 V to 1.3 V
- VDDIO:
- 3.3 V option: -0.3 V to 3.8 V
- 2.5 V option: -0.3 V to 3 V
- 1.8 V option: -0.3 V to 2.1 V
- Pins:
- MDI: -0.3 V to 6.5 V
- MAC interface / MDIO / MDC / GPIO: -0.3 V to VDDIO + 0.3
- INT/PWDN, RESET: -0.3 V to VDDIO + 0.3
- JTAG: -0.3 V to VDDIO + 0.3
- XI: -0.3 V to 2.1 V
- Storage temperature: -60 C to 150 C
- VDDA2P5: 2.375 V min, 2.5 V typ, 2.625 V max
- VDDA1P8: 1.71 V min, 1.8 V typ, 1.89 V max
- VDD1P0: 0.95 V min, 1.0 V typ, 1.155 V max
- VDDIO (options):
- 3.3 V: 3.15 / 3.3 / 3.45 V
- 2.5 V: 2.375 / 2.5 / 2.625 V
- 1.8 V: 1.71 / 1.8 / 1.89 V
- Temperature (DP83867ERGZ “Extended”):
- Operating junction: -40 C to 125 C
- Operating free-air: -40 C to 105 C
- RBIAS: “A 11 kohm +/-1% resistor can be connected from RBIAS to GND.”
- VDDA2P5: each pin requires 1 uF + 0.1 uF to GND.
- VDD1P0: each pin requires 1 uF + 0.1 uF to GND.
- VDDA1P8: “No external supply is required… When unused, no connections can be made…” (and if externally supplied, each pin requires 1 uF + 0.1 uF to GND).
- VDDIO: each pin requires 1 uF + 0.1 uF to GND.
- MDIO: “requires pullup resistor… IEEE specified 1.5 kohm, but 2.2 kohm is acceptable.”
- MDC: management clock, “maximum clock rate 25 MHz.”
- RESET_N: must be held low minimum 1 us.
- INT_PWDN_N: default POWER DOWN; in interrupt mode is open-drain, TI recommends external 2.2 kohm to VDDIO.
- X_I / X_O: 25 MHz crystal/oscillator interface; XO must float if oscillator used.
- Body size: 6.85 mm to 7.15 mm (A and B)
- Pitch: 0.5 mm (lead pitch callout)
- Exposed thermal pad: 49
- Note: “The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.”
- Wake-on-LAN (WoL) magic packet detection support is described (section 7.3.1 excerpt), including CRC checking and secure-on password support.
- Pin count alignment looks consistent with the package:
- Symbol in this project includes pins 1-48 plus exposed pad 49 as PAD.
- Footprint layout node list includes a pad with terminalId 49 (name “PAD”), consistent with the exposed thermal pad 49 in the package outline.
- Several direction/type choices appear reasonable:
- RX_D0_SGMII_COP, RX_D1_SGMII_CON, RX_D2_SGMII_SOP, RX_D3_SGMII_SON are set as outputs in the symbol, aligning with the “PHY -> MAC” concept for receive-side signals in the excerpt.
- TX_D0_SGMII_SIN, TX_D1_SGMII_SIP, TX_D2, TX_D3 are inputs in the symbol, aligning with “MAC -> PHY” concept.
- Thermal pad naming vs actual net intent:
- Datasheet explicitly requires the exposed pad be soldered for “thermal and mechanical performance.” In this part project, exposed pad is represented as PAD. If the consuming design doesn’t connect PAD to GND (or whatever the datasheet requires for that EPAD in the full pin table), assembly/thermal performance can suffer.
- Duplicate power-pin terminal names:
- The symbol uses repeated designators for rails (multiple VDD1P0 terminals; multiple VDDIO; multiple VDDA2P5; multiple VDDA1P8). That’s functionally OK, but it increases the chance a user connects only one instance and misses the others. The datasheet calls out per-pin decoupling requirements for these supplies.
- Pin function completeness:
- The excerpted pin table confirms many pins, but I did not yet extract every row of Table 5-1 (full pin map) reliably via the PDF scanner. That means I cannot 100% confirm there isn’t a swapped pin number/name elsewhere (e.g., any of the GPIO/strap pins) purely from the extracted text so far.
- I can see the footprint pad list (terminalId mapping) but not enough dimensional detail (pad widths/lengths, courtyard, exposed pad solder mask/paste strategy) from the current PCB inspect output to conclusively verify it matches the RGZ0048B land pattern. If you want a strict mechanical cross-check, I can do another pass focused on pad geometry once the footprint’s pad dimensions are exposed via the layout inspector output.
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