Power Circuit Design
- Power routing (order and widths)
- 1.1 V24: J24V_IN:1 → U1:VIN (1.2 mm). Tee J24V_IN:1 → D1:1 (1.2 mm); D1:2 to nearest GND via (short path).
- 1.2 Buck hot path: U1:SW → L1:P1 (0.6 mm); L1:P2 → buck output node → +5V (1.0 mm).
- 1.3 +5V trunk: +5V node → TP_5V (0.8 mm, stub ≤ 5 mm). +5V node → U2:IN (0.6 mm).
- 1.4 +3V3 distribution: U2:OUT → +3V3 trunk (0.6 mm) → J_SDCARD:P4, U_SDLS:Vcc, C19:P1, C20:P1, R6:P2, R7:P2, TP_3V3 (branch stubs 0.4 mm, ≤ 5 mm).
- SPI microSD routing (order, widths, ≤1 via/net)
- 2.1 SCK (0.25 mm): U3:PB1 → R_SCK → U_SDLS:1A → U_SDLS:1Y → J_SDCARD:P5.
- 2.2 MOSI/DI (0.25 mm): U3:PB2 → R_MOSI → U_SDLS:2A → U_SDLS:2Y → J_SDCARD:P3.
- 2.3 MISO/DO (0.25 mm): J_SDCARD:P7 → R_MISO → U3:PB3.
- 2.4 CS (0.25 mm): U_SDLS:3Y → J_SDCARD:P2; place R6 to +3V3 at socket end.
- 2.5 CD (0.25 mm): J_SDCARD:CD → U3:PE4 with short tees to TP_SD_CD and R7:P1 near the socket.
- 2.6 Length match SCK/MOSI/MISO within ±5 mm; keep SCK shortest.
- Stitching vias (placement order)
- 3.1 Perimeter: add GND stitching vias every 12 mm around edges (start along right edge near J_SDCARD).
- 3.2 Power zone: ring U1 and L1 with vias at 3–5 mm spacing; add 2–3 near U1 GND pins.
- 3.3 LDO zone: place 4 vias tight around U2 (by IN, GND, OUT).
- 3.4 Z3 fence: via fence between J_SDCARD, U_SDLS, U4 and board edge at 5 mm pitch.
- 3.5 Tie any isolated top GND islands with at least two vias each.
- Critical DRC to-fix list
- 4.1 Any +3V3/SD_CS/SD_CD nodes still tied to GND.
- 4.2 Power widths: V24 1 via; any airwires on SCK/MOSI/MISO/CS/CD.
- 4.4 SCK/MOSI/MISO length mismatch exceeding ±5 mm.
- 4.5 Any via/copper in MCU crystal keep-out.
Started implementing a plan
#Goal
- Reassign specific microSD interface pins from the ground net to the appropriate power (+3V3) and control nets (SD_CS and SD_CD) to eliminate shorts and align with design intent for a 2-layer board featuring the MEM2085 microSD socket, 74LVC125APW level shifter, ESD224DQA, and ATmega2560-16AU MCU.
#Implementation plan
1. Disconnect specified pins from the GND net:
1. Identify pins listed for modification (J_SDCARD:P4, TP_3V3, U_SDLS:Vcc, C19:P1, C20:P1, R6:P2, R7:P2 for +3V3; U_SDLS:3Y, J_SDCARD:P2, R6:P1 for SD_CS; J_SDCARD:CD, U3:PE4, TP_SD_CD, R7:P1 for SD_CD).
2. Sever their connection to the GND net in the schematic.
2. Connect pins to the +3V3 net:
1. Reassign J_SDCARD:P4, TP_3V3, U_SDLS:Vcc, C19:P1, C20:P1, R6:P2, and R7:P2 to the +3V3 net by creating net connections to +3V3.
3. Route SD control nets:
1. Connect SD_CS net by assigning U_SDLS:3Y, J_SDCARD:P2, and R6:P1 to SD_CS.
2. Connect SD_CD net by assigning J_SDCARD:CD, U3:PE4, TP_SD_CD, and R7:P1 to SD_CD.
4. Validate all changes:
1. Perform a quick ERC to ensure that no extra ground portals remain and that there are no connectivity errors.
2. Confirm that the netlist reflects the intended topology with the new power and control nets.
#Success criteria
- All specified pins are removed from the GND net and properly connected to either +3V3, SD_CS, or SD_CD as required.
- ERC passes without additional errors and the netlist accurately represents the desired connectivity changes.
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