NEXUS S3 Redesign
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NEXUS-S3 Universal Platform Architecture v5.4
NEXUS-S3 is defined as a Universal Embedded Computing and Control Platform, not as a robot controller. Robotics, industrial control, edge AI...
أعدت تعريف المشروع بالكامل كمنصة عامة في NEXUS‑S3 Universal Platform Architecture v5.4.
تم فصل المنصة عن التطبيق، ونقل المحركات وLTE وLoRa والكاميرا إلى وحدات اختيارية، مع إنشاء Capability Matrix وفئات توسعة وطاقة واضحة. لم أبدأ اختيار المكونات أو الـschematic.
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سأقرأ الملف كاملًا، وأحوّل ما فيه إلى تحديث معماري منظم للمشروع دون بدء اختيار المكونات أو الـschematic ما لم يطلب النص ذلك صراحةً.
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تم تثبيت حدود Standard Tier وتسمية المشروع رسميًا. يجري الآن إعداد جداول الأرجل والقواعد الكهربائية والميكانيكية لكل واجهة، ثم سأراجع عدم تكرار الأرجل واتساق تسلسل الطاقة قبل التسليم.
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اكتملت Phase 1 وتمت مراجعة ترقيم الأرجل، حدود الطاقة، الحماية، التسلسل والتوافق في NEXUS‑S3 Interface Control Specification v1.0.
تشمل PMI وPPI وLSX وHSX وAPI وجميع الموصلات الخارجية. توقفت قبل Phase 2 Power Budget كما طُلب؛ وتحتاج افتراضات وقضايا Section 14 إلى اعتمادك قبل المتابعة.
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NEXUS-S3 Functional Topology Selection v1.0
Phase: 3B — Functional Topology Selection
Platform tier: Standard Platform Tier
Status: Production-intent topology recommendation for Lead-Architect Review
Normative inputs: Interface Control Specification v1.0, Four-State Power Budget v1.0, Functional Schematic Architecture v1.0, Architecture Decision Record v1.0
Platform tier: Standard Platform Tier
Status: Production-intent topology recommendation for Lead-Architect Review
Normative inputs: Interface Control Specification v1.0, Four-State Power Budget v1.0, Functional Schematic Architecture v1.0, Architecture Decision Record v1.0
Scope boundary: This study selects architectural topologies only. It does not select ICs, manufacturer part numbers, exact component values, BOM items, footprints, detailed schematics, or PCB layout. Candidate names describe circuit and control structures, not products.
1. Evaluation method
Each candidate is evaluated using the following qualitative scale:
- Reliability: High / Medium / Low expected robustness and fault containment.
- Thermal: Low / Medium / High expected dissipation or hotspot burden, where Low is preferable.
- Scalability: High / Medium / Low ability to support future tiers and revisions.
- Manufacturing complexity: Low / Medium / High assembly/test burden.
- PCB complexity: Low / Medium / High routing, area, EMI, and layer burden.
- Debuggability: High / Medium / Low observability and fault isolation.
- Maintainability: High / Medium / Low lifecycle and serviceability.
- Engineering risk: Low / Medium / High uncertainty before detailed design and validation.
Selection priorities, in order:
- Safety and deterministic fault containment.
- Compliance with the one-source 90 W continuous envelope and conditional battery-assisted peak.
- Preservation of PIB/CCB and PMI/PPI boundaries.
- Controlled startup, shutdown, reverse energy, and unpowered-peer behavior.
- Thermal and EMI practicality on two 115 × 80 mm boards.
- Upgradeability and long-term platform compatibility.
- Manufacturing, validation, and service simplicity.
2. USB-C Input Protection and Power Path
Functional objective
Independently accept USB-C SPR contracts on Input A and Input B; protect each connector and source from ESD, surge, overvoltage, undervoltage, inrush, short circuit, and reverse current; expose a validated isolated source node to arbitration. No passive port paralleling or output sourcing is permitted.
Candidate A — Passive fuse/diode front end plus downstream switch
Each port uses passive current interruption and diode isolation followed by a controlled switch.
Advantages: Simple control; predictable open-circuit isolation; low firmware dependence.
Disadvantages: High conduction loss at 5 A; poor source/cable margin; weak precision inrush/OV response; replacement may be required after severe faults.
Reliability: Medium. Thermal: High. Scalability: Low. Manufacturing: Low–Medium. PCB: Low. Debuggability: Medium. Maintainability: Medium. Future evolution: Poor for higher power. Risk: Medium.
Disadvantages: High conduction loss at 5 A; poor source/cable margin; weak precision inrush/OV response; replacement may be required after severe faults.
Reliability: Medium. Thermal: High. Scalability: Low. Manufacturing: Low–Medium. PCB: Low. Debuggability: Medium. Maintainability: Medium. Future evolution: Poor for higher power. Risk: Medium.
Candidate B — Per-port active hot-swap/e-fuse topology with back-to-back isolation
Each port terminates into a controlled input path providing programmable inrush, electronic current limiting, over/undervoltage qualification, reverse-current blocking, telemetry, and hard isolation.
Advantages: Low loss relative to diode isolation; deterministic inrush; independent fault isolation; observable current/voltage; supports source transfer and controlled retries.
Disadvantages: More control interactions; requires SOA/thermal validation and careful transient layout.
Reliability: High. Thermal: Low–Medium. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong; can migrate with bus class. Risk: Low–Medium.
Disadvantages: More control interactions; requires SOA/thermal validation and careful transient layout.
Reliability: High. Thermal: Low–Medium. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong; can migrate with bus class. Risk: Low–Medium.
Ports receive basic reverse isolation, then share one downstream hot-swap/protection stage.
Advantages: Reduced duplicated high-power protection.
Disadvantages: Shared fault domain; weaker per-port diagnosis; source-transfer events stress common stage; a common failure may disable both inputs.
Reliability: Medium. Thermal: Medium. Scalability: Medium. Manufacturing: Medium. PCB: Medium. Debuggability: Medium. Maintainability: Medium. Future evolution: Moderate. Risk: Medium–High.
Disadvantages: Shared fault domain; weaker per-port diagnosis; source-transfer events stress common stage; a common failure may disable both inputs.
Reliability: Medium. Thermal: Medium. Scalability: Medium. Manufacturing: Medium. PCB: Medium. Debuggability: Medium. Maintainability: Medium. Future evolution: Moderate. Risk: Medium–High.
Preferred topology
Candidate B: independent active per-port hot-swap/e-fuse paths with back-to-back isolation. It best preserves port independence, prevents cross-feed, controls 5 A attach current, enables accurate source budgeting, and confines a fault to one input. The two paths shall be functionally symmetrical and separately monitored.
3. Source Arbitration
Functional objective
Select one qualified USB-C source at a time, permit controlled handover, coordinate optional battery support, and prevent cross-conduction. Aggregation is excluded.
Candidate A — Fixed-priority diode-OR arbitration
Input A always wins when valid; diode OR provides automatic fallback.
Advantages: Simple, fast, little control logic.
Disadvantages: Conduction loss; no intelligent source-quality selection; potential chatter; poor telemetry and controlled break-before-make.
Reliability: Medium. Thermal: High. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: Low. Maintainability: Medium. Future evolution: Weak. Risk: Medium.
Disadvantages: Conduction loss; no intelligent source-quality selection; potential chatter; poor telemetry and controlled break-before-make.
Reliability: Medium. Thermal: High. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: Low. Maintainability: Medium. Future evolution: Weak. Risk: Medium.
Candidate B — Active ideal-diode OR with autonomous highest/first-valid selection
Both paths remain isolated and an analog policy automatically connects the preferred valid source.
Advantages: Low loss; fast failover; limited firmware dependence.
Disadvantages: Autonomous decisions can conflict with PD capability, battery policy, thermal limits, or graceful transfer objectives; oscillation/chatter requires care.
Reliability: High. Thermal: Low. Scalability: Medium. Manufacturing: Medium. PCB: Medium. Debuggability: Medium. Maintainability: Medium. Future evolution: Moderate. Risk: Medium.
Disadvantages: Autonomous decisions can conflict with PD capability, battery policy, thermal limits, or graceful transfer objectives; oscillation/chatter requires care.
Reliability: High. Thermal: Low. Scalability: Medium. Manufacturing: Medium. PCB: Medium. Debuggability: Medium. Maintainability: Medium. Future evolution: Moderate. Risk: Medium.
Candidate C — Supervisor-commanded break-before-make arbitration with hardware interlock
The PIB supervisor chooses the source using negotiated capability, voltage, current, temperature, and fault history. Hardware logic prevents simultaneous connection and provides autonomous emergency disconnection.
Advantages: Explicit no-aggregation guarantee; policy-aware selection; controlled transfer; excellent logging and degraded-source behavior.
Disadvantages: More state logic; requires AON availability and careful transfer/hold-up design.
Reliability: High. Thermal: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low–Medium.
Disadvantages: More state logic; requires AON availability and careful transfer/hold-up design.
Reliability: High. Thermal: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low–Medium.
Preferred topology
Candidate C: supervisor-commanded break-before-make arbitration with independent hardware cross-conduction interlock. Hardware retains immediate fault isolation; software/policy selects only among already validated paths. A small ride-through domain shall bridge legal transfer gaps without source paralleling.
4. Protected System Bus
Functional objective
Create an 18–21 V working distribution domain that receives the selected USB source and optional battery energy, supports 90 W continuous operation, contains transients, and feeds independently controlled downstream domains.
Candidate A — Unregulated selected-source bus
The chosen 20 V PD source directly defines the protected bus after switching/protection.
Advantages: Highest efficiency, lowest part count, no central switching EMI.
Disadvantages: Bus follows 5/9/15/20 V source contracts; incompatible with a stable 20 V-class API and fixed downstream assumptions; source transfer causes wider excursions.
Reliability: High for simplicity. Thermal: Low. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: High. Maintainability: High. Future evolution: Weak. Risk: High due to functional mismatch.
Disadvantages: Bus follows 5/9/15/20 V source contracts; incompatible with a stable 20 V-class API and fixed downstream assumptions; source transfer causes wider excursions.
Reliability: High for simplicity. Thermal: Low. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: High. Maintainability: High. Future evolution: Weak. Risk: High due to functional mismatch.
Candidate B — Central regulated non-isolated buck-boost bus
All accepted USB contracts and battery voltages are converted to a regulated 20 V-class bus.
Advantages: Stable bus across sources; clean downstream contracts; supports battery configurations above/below bus; controlled transitions.
Disadvantages: Full platform power passes through a high-power converter; loss, EMI, thermal concentration, cost, and control complexity increase.
Reliability: Medium–High. Thermal: High. Scalability: High. Manufacturing: High. PCB: High. Debuggability: Medium. Maintainability: Medium. Future evolution: Strong. Risk: High.
Disadvantages: Full platform power passes through a high-power converter; loss, EMI, thermal concentration, cost, and control complexity increase.
Reliability: Medium–High. Thermal: High. Scalability: High. Manufacturing: High. PCB: High. Debuggability: Medium. Maintainability: Medium. Future evolution: Strong. Risk: High.
Candidate C — Hybrid bus: direct protected 20 V pass-through with conversion only for non-20 V or battery modes
A valid 20 V PD source feeds the bus through a low-loss path; lower-voltage contracts support restricted operation through a bounded conversion path or do not energize the full bus. Battery interfaces through a controlled bidirectional converter as required by pack voltage.
Advantages: Efficient normal 20 V operation; stable full-power contract; conversion loss occurs only in degraded/battery modes; preserves low-power startup from lesser contracts.
Disadvantages: Multiple operating modes and transition paths; lower contracts cannot promise full functionality; control verification is more complex than a single bus converter.
Reliability: High. Thermal: Low–Medium normal, Medium–High converted mode. Scalability: High. Manufacturing: Medium–High. PCB: Medium–High. Debuggability: High with mode telemetry. Maintainability: High. Future evolution: Strong. Risk: Medium.
Disadvantages: Multiple operating modes and transition paths; lower contracts cannot promise full functionality; control verification is more complex than a single bus converter.
Reliability: High. Thermal: Low–Medium normal, Medium–High converted mode. Scalability: High. Manufacturing: Medium–High. PCB: Medium–High. Debuggability: High with mode telemetry. Maintainability: High. Future evolution: Strong. Risk: Medium.
Preferred topology
Candidate C: hybrid protected bus. Full Standard Tier operation requires a qualified 20 V contract and uses low-loss pass-through. Lower contracts power AON and restricted/limited modes through a bounded conversion path. The optional battery path regulates energy exchange as needed. This avoids wasting several watts in normal 90 W operation while preserving controlled degraded behavior.
5. Battery Path
Functional objective
On battery SKUs, accept only a qualified pack, coordinate BMS protection, charge from available external power, support controlled discharge/UPS and optional short peak assist, and isolate unknown or faulted packs.
Candidate A — Pack directly ORed to the system bus with separate charger
Battery discharge is diode/ideal-diode connected to the bus; charging uses a separate unidirectional path.
Advantages: Simple discharge continuity; fast takeover.
Disadvantages: Pack voltage must closely match bus; poor control of energy flow; difficult peak limiting; charger and discharge paths can interact; arbitrary pack constraints.
Reliability: Medium. Thermal: Medium. Scalability: Low. Manufacturing: Medium. PCB: Medium. Debuggability: Medium. Maintainability: Low. Future evolution: Weak. Risk: High.
Disadvantages: Pack voltage must closely match bus; poor control of energy flow; difficult peak limiting; charger and discharge paths can interact; arbitrary pack constraints.
Reliability: Medium. Thermal: Medium. Scalability: Low. Manufacturing: Medium. PCB: Medium. Debuggability: Medium. Maintainability: Low. Future evolution: Weak. Risk: High.
Candidate B — Separate unidirectional charger plus controlled boost discharge path
Pack charges through one path and discharges through another regulated path.
Advantages: Clear direction-specific control; can support pack below bus; independent optimization.
Disadvantages: Duplicate power stages; no seamless bidirectional sharing without coordination; more area and loss.
Reliability: Medium–High. Thermal: High. Scalability: Medium. Manufacturing: High. PCB: High. Debuggability: High. Maintainability: Medium. Future evolution: Moderate. Risk: Medium–High.
Disadvantages: Duplicate power stages; no seamless bidirectional sharing without coordination; more area and loss.
Reliability: Medium–High. Thermal: High. Scalability: Medium. Manufacturing: High. PCB: High. Debuggability: High. Maintainability: Medium. Future evolution: Moderate. Risk: Medium–High.
Candidate C — Single controlled bidirectional buck-boost battery power path with precharge and hard isolation
One reversible conversion path regulates charge and discharge, enforces current/voltage/temperature policy, and supports controlled UPS/peak assistance.
Advantages: Best energy-flow control; broad pack-voltage compatibility within a frozen class; seamless handover; measured peak assist; explicit isolation.
Disadvantages: Highest control-loop and validation complexity; full battery power passes through a switching stage; cannot be finalized until pack class is frozen.
Reliability: High after qualification. Thermal: Medium–High. Scalability: High. Manufacturing: High. PCB: High. Debuggability: High. Maintainability: High with telemetry. Future evolution: Strong. Risk: High until pack requirements close.
Disadvantages: Highest control-loop and validation complexity; full battery power passes through a switching stage; cannot be finalized until pack class is frozen.
Reliability: High after qualification. Thermal: Medium–High. Scalability: High. Manufacturing: High. PCB: High. Debuggability: High. Maintainability: High with telemetry. Future evolution: Strong. Risk: High until pack requirements close.
Preferred topology
Candidate C: controlled bidirectional buck-boost path with connector precharge, back-to-back isolation, pack ID/temperature validation, and independent BMS. It is the only topology aligned with optional UPS, full charging, and bounded peak assist without tying the platform to a narrow pack voltage. Phase 4 remains blocked until battery class is frozen.
6. AON Supply Architecture
Functional objective
Power the PIB safety supervisor, source detection, sequencing, fault retention, and discovery logic whenever any valid source exists, with low standby draw and operation across supported source/battery conditions.
Candidate A — Single linear regulator from bus
Advantages: Very low noise, simple, easy debug.
Disadvantages: Excessive loss from 20 V to low voltage; poor thermal behavior; weak battery efficiency.
Reliability: High at low current. Thermal: Medium–High. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: High. Maintainability: High. Future evolution: Weak. Risk: Medium.
Disadvantages: Excessive loss from 20 V to low voltage; poor thermal behavior; weak battery efficiency.
Reliability: High at low current. Thermal: Medium–High. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: High. Maintainability: High. Future evolution: Weak. Risk: Medium.
Candidate B — Single always-on high-voltage buck directly to one logic rail
Advantages: Efficient across bus range; simple rail tree; supports modest discovery loads.
Disadvantages: Switching noise in safety domain; light-load efficiency and startup behavior require care; one rail fault can affect all AON functions.
Reliability: High. Thermal: Low. Scalability: Medium. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Good. Risk: Low–Medium.
Disadvantages: Switching noise in safety domain; light-load efficiency and startup behavior require care; one rail fault can affect all AON functions.
Reliability: High. Thermal: Low. Scalability: Medium. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Good. Risk: Low–Medium.
Candidate C — Two-stage AON: efficient high-voltage preregulator plus quiet/segmented low-voltage rails
A high-efficiency stage produces an intermediate AON rail; local quiet regulation or filtering feeds supervisor/reference/analog functions, with separately current-limited discovery branches.
Advantages: Efficiency plus low-noise critical rails; discovery faults can be isolated; flexible retention domains.
Disadvantages: More stages, quiescent contributors, and sequence dependencies.
Reliability: High. Thermal: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low–Medium.
Disadvantages: More stages, quiescent contributors, and sequence dependencies.
Reliability: High. Thermal: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low–Medium.
Preferred topology
Candidate C: two-stage segmented AON architecture. Use efficient high-voltage conversion followed by quiet local regulation/filtering for safety references and separately limited discovery outputs. The topology minimizes 20 V linear loss while ensuring module faults cannot collapse the supervisor.
7. Core 5 V Generation
Functional objective
Generate PPI
CORE_5V at 5 A continuous and 7 A/100 ms transient from the 18–21 V bus with controlled startup, current measurement, PG, discharge, and high efficiency.Candidate A — Single-phase synchronous buck
Advantages: Lowest complexity and area; one control loop; high efficiency at moderate loads.
Disadvantages: High inductor/switch ripple and hotspot at 5–7 A; input/output capacitor stress; less graceful scaling.
Reliability: High. Thermal: Medium–High. Scalability: Medium. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Moderate. Risk: Low–Medium.
Disadvantages: High inductor/switch ripple and hotspot at 5–7 A; input/output capacitor stress; less graceful scaling.
Reliability: High. Thermal: Medium–High. Scalability: Medium. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Moderate. Risk: Low–Medium.
Candidate B — Interleaved multiphase synchronous buck
Two or more phases share current and cancel ripple.
Advantages: Lower per-phase thermal stress and ripple; excellent transient response; scalable to future Core power.
Disadvantages: Higher cost, area, control and current-sharing complexity; may be inefficient at light load unless phases shed.
Reliability: High with proper sharing. Thermal: Low–Medium. Scalability: High. Manufacturing: High. PCB: High. Debuggability: Medium. Maintainability: Medium. Future evolution: Strong. Risk: Medium.
Disadvantages: Higher cost, area, control and current-sharing complexity; may be inefficient at light load unless phases shed.
Reliability: High with proper sharing. Thermal: Low–Medium. Scalability: High. Manufacturing: High. PCB: High. Debuggability: Medium. Maintainability: Medium. Future evolution: Strong. Risk: Medium.
Candidate C — Distributed two-stage Core input conversion
PIB sends a higher intermediate rail; CCB generates 5 V or direct local rails.
Advantages: Moves some heat to CCB and can reduce low-voltage connector current.
Disadvantages: Contradicts frozen PPI 5 V contract; ties CCB generations to a revised interface; duplicates conversion and complicates compatibility.
Reliability: Medium. Thermal: Distributed. Scalability: Medium. Manufacturing: High. PCB: High. Debuggability: Medium. Maintainability: Low. Future evolution: Requires PPI revision. Risk: High.
Disadvantages: Contradicts frozen PPI 5 V contract; ties CCB generations to a revised interface; duplicates conversion and complicates compatibility.
Reliability: Medium. Thermal: Distributed. Scalability: Medium. Manufacturing: High. PCB: High. Debuggability: Medium. Maintainability: Low. Future evolution: Requires PPI revision. Risk: High.
Preferred topology
Candidate A for Standard Tier: a single-phase synchronous buck with load-step-appropriate energy storage and strong thermal spreading. The 25 W Core ceiling does not justify multiphase complexity for the base tier. The architecture shall reserve a migration path to interleaved multiphase in a higher-power PIB revision without changing PPI semantics.
8. Local POL Strategy
Functional objective
Generate Core-specific digital, memory/I/O, analog, RF, sensor, and peripheral rails locally from CCB 5 V with correct sequencing, noise, efficiency, and fault containment.
Candidate A — One centralized multi-output conversion cluster
Advantages: Compact control and sequencing; potentially low component count.
Disadvantages: Tightly couples future processors to one architecture; shared thermal hotspot; cross-rail fault dependence; difficult local noise optimization.
Reliability: Medium. Thermal: High concentration. Scalability: Low–Medium. Manufacturing: Medium. PCB: Medium. Debuggability: Medium. Maintainability: Low. Future evolution: Weak. Risk: Medium.
Disadvantages: Tightly couples future processors to one architecture; shared thermal hotspot; cross-rail fault dependence; difficult local noise optimization.
Reliability: Medium. Thermal: High concentration. Scalability: Low–Medium. Manufacturing: Medium. PCB: Medium. Debuggability: Medium. Maintainability: Low. Future evolution: Weak. Risk: Medium.
Candidate B — Fully distributed independent converters at every load
Advantages: Best local regulation and modularity; each rail optimized independently.
Disadvantages: Many switching nodes, EMI sources, enable/PG signals, and duplicated passives; complex validation.
Reliability: High fault isolation. Thermal: Distributed. Scalability: High. Manufacturing: High. PCB: High. Debuggability: High. Maintainability: Medium. Future evolution: Strong. Risk: Medium–High.
Disadvantages: Many switching nodes, EMI sources, enable/PG signals, and duplicated passives; complex validation.
Reliability: High fault isolation. Thermal: Distributed. Scalability: High. Manufacturing: High. PCB: High. Debuggability: High. Maintainability: Medium. Future evolution: Strong. Risk: Medium–High.
Candidate C — Hierarchical mixed POL: efficient switching for power rails, quiet post-regulation/filtering for sensitive rails, switched load domains
Advantages: Balances efficiency, noise, sequencing and modularity; isolates analog/RF; permits per-domain shutdown; adaptable to processor changes.
Disadvantages: More architectural planning and rail dependencies; some duplicate stages.
Reliability: High. Thermal: Low–Medium distributed. Scalability: High. Manufacturing: Medium–High. PCB: Medium–High. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low–Medium.
Disadvantages: More architectural planning and rail dependencies; some duplicate stages.
Reliability: High. Thermal: Low–Medium distributed. Scalability: High. Manufacturing: Medium–High. PCB: Medium–High. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low–Medium.
Preferred topology
Candidate C: hierarchical mixed POL. High-current digital/memory rails use efficient local switching; low-noise analog/RF rails use dedicated filtering or post-regulation; sensor/peripheral rails use current-limited load switches. Rail grouping and sequence remain compute-tier-specific but PPI remains stable.
9. API Power Path
Functional objective
Deliver a bounded 18–21 V application rail, 5 A continuous and 8 A/100 ms transient, with discovery, precharge, hard disconnect, current/thermal monitoring, reverse-current blocking, and emergency inhibit.
Candidate A — Single high-side switch with current limit
Advantages: Simple, low loss, easy control.
Disadvantages: Limited inrush and reverse protection sophistication; single switch may not isolate all failure modes; difficult 160 W pulse SOA.
Reliability: Medium. Thermal: Medium. Scalability: Low. Manufacturing: Low–Medium. PCB: Medium. Debuggability: Medium. Maintainability: Medium. Future evolution: Weak. Risk: High.
Disadvantages: Limited inrush and reverse protection sophistication; single switch may not isolate all failure modes; difficult 160 W pulse SOA.
Reliability: Medium. Thermal: Medium. Scalability: Low. Manufacturing: Low–Medium. PCB: Medium. Debuggability: Medium. Maintainability: Medium. Future evolution: Weak. Risk: High.
Candidate B — Back-to-back disconnect with separate precharge and shunt-based monitoring
Main bidirectional-blocking switches remain open while a limited precharge path charges declared module capacitance; hardware current/voltage/temperature thresholds govern closure and faults.
Advantages: Deterministic inrush; full reverse blocking; high observability; emergency isolation; scalable switch area; supports latched fault policy.
Disadvantages: More control states and thermal/SOA validation; larger PCB area.
Reliability: High. Thermal: Low–Medium normal, High transient. Scalability: High. Manufacturing: Medium–High. PCB: High. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Medium.
Disadvantages: More control states and thermal/SOA validation; larger PCB area.
Reliability: High. Thermal: Low–Medium normal, High transient. Scalability: High. Manufacturing: Medium–High. PCB: High. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Medium.
Candidate C — Fully regulated isolated or non-isolated API converter
Advantages: Stable output and strong separation from bus disturbances; possible galvanic isolation.
Disadvantages: A 100–160 W converter adds major loss, size, heat and cost; unnecessary for same-voltage v1.0 API; isolated return conflicts with current grounding baseline unless required.
Reliability: Medium–High. Thermal: High. Scalability: Medium. Manufacturing: High. PCB: High. Debuggability: Medium. Maintainability: Medium. Future evolution: Specialized. Risk: High.
Disadvantages: A 100–160 W converter adds major loss, size, heat and cost; unnecessary for same-voltage v1.0 API; isolated return conflicts with current grounding baseline unless required.
Reliability: Medium–High. Thermal: High. Scalability: Medium. Manufacturing: High. PCB: High. Debuggability: Medium. Maintainability: Medium. Future evolution: Specialized. Risk: High.
Preferred topology
Candidate B: back-to-back hard disconnect plus limited precharge, low-loss current sense, local hardware trip, discharge, and PIB-controlled enable. API v1.0 remains bus-following and unidirectional. A future isolated/regenerative variant requires a new interface revision.
10. AUX Rail Generation
Functional objective
Provide protected 12 V/1 A and 5 V/1 A external auxiliary outputs, combined ≤12 W, with independent fault isolation and default-off behavior.
Candidate A — Separate dedicated buck converter for each rail
Advantages: Independent regulation and faults; simple rail behavior; good efficiency.
Disadvantages: Duplicate switching stages, area and EMI sources.
Reliability: High. Thermal: Low–Medium. Scalability: High. Manufacturing: Medium–High. PCB: Medium–High. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low.
Disadvantages: Duplicate switching stages, area and EMI sources.
Reliability: High. Thermal: Low–Medium. Scalability: High. Manufacturing: Medium–High. PCB: Medium–High. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low.
Candidate B — 12 V primary buck with cascaded 5 V buck
Advantages: Reduced direct 20 V switching on 5 V stage; possible component/EMI simplification.
Disadvantages: 5 V depends on 12 V; double conversion loss; 12 V fault can remove both rails.
Reliability: Medium. Thermal: Medium. Scalability: Medium. Manufacturing: Medium. PCB: Medium. Debuggability: Medium. Maintainability: Medium. Future evolution: Moderate. Risk: Medium.
Disadvantages: 5 V depends on 12 V; double conversion loss; 12 V fault can remove both rails.
Reliability: Medium. Thermal: Medium. Scalability: Medium. Manufacturing: Medium. PCB: Medium. Debuggability: Medium. Maintainability: Medium. Future evolution: Moderate. Risk: Medium.
Candidate C — Single multi-output coupled conversion stage
Advantages: Potentially compact and synchronized.
Disadvantages: Cross-regulation, coupled faults, limited independent enable/current limits, difficult application-neutral behavior.
Reliability: Medium. Thermal: Medium. Scalability: Low. Manufacturing: Medium. PCB: Medium. Debuggability: Low. Maintainability: Low. Future evolution: Weak. Risk: High.
Disadvantages: Cross-regulation, coupled faults, limited independent enable/current limits, difficult application-neutral behavior.
Reliability: Medium. Thermal: Medium. Scalability: Low. Manufacturing: Medium. PCB: Medium. Debuggability: Low. Maintainability: Low. Future evolution: Weak. Risk: High.
Preferred topology
Candidate A: separate independently enabled synchronous buck rails with per-output load isolation, current monitoring, discharge, and fault reporting. At only 12 W combined, independence and serviceability outweigh duplicated stages.
11. LSX Power Distribution
Functional objective
Provide 3.3 V restricted discovery, then bounded full 5 V and 3.3 V module rails; isolate rejected/unpowered modules and contain faults.
Advantages: Simple and low cost.
Disadvantages: Violates restricted discovery; one module can collapse all; back-power and hot-attach risk.
Reliability: Low. Thermal: Low. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: Low. Maintainability: Low. Future evolution: Poor. Risk: High.
Disadvantages: Violates restricted discovery; one module can collapse all; back-power and hot-attach risk.
Reliability: Low. Thermal: Low. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: Low. Maintainability: Low. Future evolution: Poor. Risk: High.
Advantages: Good per-port isolation; centralized conversion; manageable area.
Disadvantages: Shared converter remains common fault/capacity point; 3.3 V and 5 V allocation interactions require care.
Reliability: High. Thermal: Low–Medium. Scalability: Medium–High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Good. Risk: Low.
Disadvantages: Shared converter remains common fault/capacity point; 3.3 V and 5 V allocation interactions require care.
Reliability: High. Thermal: Low–Medium. Scalability: Medium–High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Good. Risk: Low.
Candidate C — Dedicated conversion per LSX port
Advantages: Maximum isolation and voltage flexibility.
Disadvantages: Excess stages, area, EMI and cost for low-power modules.
Reliability: High. Thermal: Distributed. Scalability: High. Manufacturing: High. PCB: High. Debuggability: High. Maintainability: Medium. Future evolution: Strong. Risk: Medium.
Disadvantages: Excess stages, area, EMI and cost for low-power modules.
Reliability: High. Thermal: Distributed. Scalability: High. Manufacturing: High. PCB: High. Debuggability: High. Maintainability: Medium. Future evolution: Strong. Risk: Medium.
Preferred topology
Candidate B: centralized LSX full-rail generation with a separately current-limited discovery rail and per-port load switches/current limits/signal isolation. If only one LSX connector exists, the same structure remains valuable for deterministic discovery and fault containment.
12. HSX Power Distribution
Functional objective
Provide 3.3 V/100 mA discovery and 5 V up to 5 A full module power with strict reset/clock ordering, low impedance, inrush control, and thermal fault containment.
Candidate A — Direct connection to CCB 5 V with module-controlled startup
Advantages: Lowest loss and area.
Disadvantages: No host inrush/fault authority; violates discovery-first policy; module short can collapse Core.
Reliability: Low. Thermal: Low. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: Low. Maintainability: Low. Future evolution: Poor. Risk: High.
Disadvantages: No host inrush/fault authority; violates discovery-first policy; module short can collapse Core.
Reliability: Low. Thermal: Low. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: Low. Maintainability: Low. Future evolution: Poor. Risk: High.
Candidate B — High-current load switch/e-fuse from CCB 5 V with discovery branch
Advantages: Low conversion loss; controlled ramp; current/thermal protection; reset/clock can remain gated; clear telemetry.
Disadvantages: Shares upstream Core 5 V capacity; load step can disturb Core unless distribution and bulk segmentation are strong.
Reliability: High. Thermal: Low–Medium. Scalability: High within 25 W. Manufacturing: Medium. PCB: Medium–High. Debuggability: High. Maintainability: High. Future evolution: Good. Risk: Low–Medium.
Disadvantages: Shares upstream Core 5 V capacity; load step can disturb Core unless distribution and bulk segmentation are strong.
Reliability: High. Thermal: Low–Medium. Scalability: High within 25 W. Manufacturing: Medium. PCB: Medium–High. Debuggability: High. Maintainability: High. Future evolution: Good. Risk: Low–Medium.
Candidate C — Dedicated HSX 5 V converter from optional PPI 12 V or another intermediate rail
Advantages: Better isolation from Core 5 V load steps; distributes power conversion.
Disadvantages: Relies on optional PPI AUX_12V or revised rail; adds conversion loss and CCB thermal burden.
Reliability: High. Thermal: Medium–High. Scalability: High. Manufacturing: High. PCB: High. Debuggability: High. Maintainability: Medium. Future evolution: Requires stable PPI policy. Risk: Medium–High.
Disadvantages: Relies on optional PPI AUX_12V or revised rail; adds conversion loss and CCB thermal burden.
Reliability: High. Thermal: Medium–High. Scalability: High. Manufacturing: High. PCB: High. Debuggability: High. Maintainability: Medium. Future evolution: Requires stable PPI policy. Risk: Medium–High.
Preferred topology
Candidate B: protected high-current load-switch/e-fuse distribution from CCB 5 V with dedicated discovery, bulk segmentation, current telemetry, thermal alert, reset and reference-clock gating. Phase 3B does not require populating PPI AUX_12V for HSX.
13. Current Measurement Strategy
Functional objective
Measure source, bus, battery, Core, API, and expansion currents accurately enough for protection, allocation, telemetry, and diagnostics without excessive loss.
Candidate A — High-side shunt measurement everywhere
Advantages: Ground remains undisturbed; detects current direction; familiar and accurate.
Disadvantages: Insertion loss at high currents; common-mode range complexity; many amplifiers/monitors; heat at API/bus peaks.
Reliability: High. Thermal: Medium. Scalability: Medium. Manufacturing: Medium. PCB: Medium–High. Debuggability: High. Maintainability: High. Future evolution: Good. Risk: Low–Medium.
Disadvantages: Insertion loss at high currents; common-mode range complexity; many amplifiers/monitors; heat at API/bus peaks.
Reliability: High. Thermal: Medium. Scalability: Medium. Manufacturing: Medium. PCB: Medium–High. Debuggability: High. Maintainability: High. Future evolution: Good. Risk: Low–Medium.
Candidate B — Low-side shunt measurement everywhere
Advantages: Simple sensing and common-mode requirements; low cost.
Disadvantages: Disturbs ground references; unsuitable for mixed signal/high-speed and connector return integrity; can miss alternate return paths.
Reliability: Medium. Thermal: Medium. Scalability: Low. Manufacturing: Low. PCB: Medium. Debuggability: Medium. Maintainability: Medium. Future evolution: Weak. Risk: High.
Disadvantages: Disturbs ground references; unsuitable for mixed signal/high-speed and connector return integrity; can miss alternate return paths.
Reliability: Medium. Thermal: Medium. Scalability: Low. Manufacturing: Low. PCB: Medium. Debuggability: Medium. Maintainability: Medium. Future evolution: Weak. Risk: High.
Candidate C — Hybrid sensing: high-side precision shunts for allocation, fast lossless/low-loss protection sensing where necessary, indirect telemetry for minor rails
Advantages: Optimizes accuracy, bandwidth and dissipation per domain; separates fast trips from metering; reduces unnecessary sensors.
Disadvantages: Multiple sensing methods require calibration and consistent data semantics.
Reliability: High. Thermal: Low–Medium. Scalability: High. Manufacturing: Medium–High. PCB: Medium–High. Debuggability: High. Maintainability: High with documented calibration. Future evolution: Strong. Risk: Medium.
Disadvantages: Multiple sensing methods require calibration and consistent data semantics.
Reliability: High. Thermal: Low–Medium. Scalability: High. Manufacturing: Medium–High. PCB: Medium–High. Debuggability: High. Maintainability: High with documented calibration. Future evolution: Strong. Risk: Medium.
Preferred topology
Candidate C: hybrid strategy. Use high-side bidirectional shunt telemetry at USB paths, battery, protected bus, Core 5 V, API, LSX, and HSX; use an independent fast analog overcurrent path at destructive-energy domains; infer or optionally measure minor POL currents. Kelvin routing and test calibration are mandatory future requirements.
14. Voltage Monitoring Strategy
Functional objective
Detect valid, warning, and destructive voltage conditions with sufficient independence for sequencing, protection, telemetry, and root-cause diagnosis.
Candidate A — Supervisor ADC-only monitoring
Advantages: Flexible thresholds, low part count, rich telemetry.
Disadvantages: Sampling latency and software dependence are unacceptable for destructive OVP/UV events; startup blind spots.
Reliability: Low–Medium. Thermal: Low. Scalability: High. Manufacturing: Low. PCB: Low. Debuggability: High. Maintainability: High. Future evolution: Good. Risk: High.
Disadvantages: Sampling latency and software dependence are unacceptable for destructive OVP/UV events; startup blind spots.
Reliability: Low–Medium. Thermal: Low. Scalability: High. Manufacturing: Low. PCB: Low. Debuggability: High. Maintainability: High. Future evolution: Good. Risk: High.
Candidate B — Dedicated hardware comparators/supervisors only
Advantages: Fast deterministic response; active before firmware.
Disadvantages: Many thresholds and parts; little waveform/history information; changing limits requires hardware revision.
Reliability: High. Thermal: Low. Scalability: Medium. Manufacturing: Medium–High. PCB: Medium. Debuggability: Medium. Maintainability: Medium. Future evolution: Moderate. Risk: Low.
Disadvantages: Many thresholds and parts; little waveform/history information; changing limits requires hardware revision.
Reliability: High. Thermal: Low. Scalability: Medium. Manufacturing: Medium–High. PCB: Medium. Debuggability: Medium. Maintainability: Medium. Future evolution: Moderate. Risk: Low.
Candidate C — Dual-path monitoring: hardware window/trip thresholds plus ADC telemetry
Advantages: Fast independent protection and rich diagnostics; warning thresholds can precede hard trips; supports calibration and trend analysis.
Disadvantages: More circuitry and threshold coordination.
Reliability: High. Thermal: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low.
Disadvantages: More circuitry and threshold coordination.
Reliability: High. Thermal: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low.
Preferred topology
Candidate C: dual-path voltage monitoring. Hardware window/trip paths protect USB inputs, bus, battery, Core 5 V and API. Supervisor ADC telemetry records continuous values and supports policy, but cannot mask hard trips.
15. Protection Strategy
Functional objective
Coordinate reverse polarity/current, inrush, OCP, OVP, UVP, short-circuit, thermal, ESD and surge protection without creating a single common fault domain.
Candidate A — Centralized protection at source and bus only
Advantages: Lower part count and easier global design.
Disadvantages: Downstream port faults can collapse the platform; cable faults lack local containment; weak service diagnosis.
Reliability: Low–Medium. Thermal: Medium. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: Low. Maintainability: Low. Future evolution: Poor. Risk: High.
Disadvantages: Downstream port faults can collapse the platform; cable faults lack local containment; weak service diagnosis.
Reliability: Low–Medium. Thermal: Medium. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: Low. Maintainability: Low. Future evolution: Poor. Risk: High.
Candidate B — Fully duplicated protection at every conversion and load
Advantages: Maximum fault isolation and layered defense.
Disadvantages: High cost, area, losses, nuisance-trip coordination, manufacturing and validation burden.
Reliability: High if coordinated. Thermal: Medium–High. Scalability: High. Manufacturing: High. PCB: High. Debuggability: High. Maintainability: Medium. Future evolution: Strong. Risk: Medium–High.
Disadvantages: High cost, area, losses, nuisance-trip coordination, manufacturing and validation burden.
Reliability: High if coordinated. Thermal: Medium–High. Scalability: High. Manufacturing: High. PCB: High. Debuggability: High. Maintainability: Medium. Future evolution: Strong. Risk: Medium–High.
Candidate C — Layered selective coordination
Connector-entry ESD/surge/miswire protection; source-path isolation; bus-level hard limits; per-rail conversion protection; per-port current limiting; local hardware trips for high-energy domains; software telemetry and bounded retry policy.
Advantages: Fault containment with rational redundancy; supports selective trip order and service diagnosis; preserves AON.
Disadvantages: Requires formal threshold/time coordination and fault-tree validation.
Reliability: High. Thermal: Low–Medium. Scalability: High. Manufacturing: Medium–High. PCB: Medium–High. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low–Medium.
Disadvantages: Requires formal threshold/time coordination and fault-tree validation.
Reliability: High. Thermal: Low–Medium. Scalability: High. Manufacturing: Medium–High. PCB: Medium–High. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low–Medium.
Preferred topology
Candidate C: layered selectively coordinated protection. Each boundary protects its conductors and fault energy; upstream stages provide backup, not routine interruption. Persistent high-energy faults latch off; limited retries apply only to qualified recoverable loads.
16. Reset Generation
Functional objective
Hold each controller and peripheral in a safe state until power, clock, compatibility, and upstream authority are valid; respond deterministically to watchdogs, brownouts, debug and faults.
Candidate A — RC power-on resets with firmware-managed downstream reset
Advantages: Simple and inexpensive.
Disadvantages: Poor threshold precision; unsafe slow ramps; no fault cause discrimination; firmware dependence.
Reliability: Low. Thermal: Low. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: Low. Maintainability: Low. Future evolution: Poor. Risk: High.
Disadvantages: Poor threshold precision; unsafe slow ramps; no fault cause discrimination; firmware dependence.
Reliability: Low. Thermal: Low. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: Low. Maintainability: Low. Future evolution: Poor. Risk: High.
Candidate B — Dedicated voltage supervisor per critical rail, wired reset tree
Advantages: Deterministic rail thresholds; independent of firmware; good brownout behavior.
Disadvantages: Many devices/signals; complex wired-OR and delay relationships; limited flexible sequencing.
Reliability: High. Thermal: Low. Scalability: Medium. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: Medium. Future evolution: Moderate. Risk: Low.
Disadvantages: Many devices/signals; complex wired-OR and delay relationships; limited flexible sequencing.
Reliability: High. Thermal: Low. Scalability: Medium. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: Medium. Future evolution: Moderate. Risk: Low.
Candidate C — Hierarchical reset architecture: hardware supervisors and reset gate, sequencer-controlled distribution, firmware-visible causes
PIB AON supervisor controls authoritative Core reset; CCB hardware supervises local rails and distributes resets; firmware may request but not bypass reset conditions.
Advantages: Strong safety boundary; scalable local sequencing; clear cause logging; supports debug and module isolation.
Disadvantages: More interfaces and formal reset dependency design.
Reliability: High. Thermal: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low.
Disadvantages: More interfaces and formal reset dependency design.
Reliability: High. Thermal: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low.
Preferred topology
Candidate C: hierarchical hardware-gated reset. PIB owns
CORE_RESET_N; CCB owns local peripheral/module resets only after Core power and clock validity. Watchdog/debug resets return API/high-power authorization to OFF.17. Clock Distribution Strategy
Functional objective
Provide independent PIB safety timing, CCB compute clocks, Ethernet and HSX references, optional synchronization, and clock-loss-safe reset behavior without selecting oscillators.
Advantages: Coherent timing and fewer sources.
Disadvantages: Cross-board SI/EMI complexity; shared single-point failure; PIB safety depends on CCB/connector clock; inflexible compute upgrades.
Reliability: Low–Medium. Thermal: Low. Scalability: Low. Manufacturing: Medium. PCB: High. Debuggability: Medium. Maintainability: Low. Future evolution: Poor. Risk: High.
Disadvantages: Cross-board SI/EMI complexity; shared single-point failure; PIB safety depends on CCB/connector clock; inflexible compute upgrades.
Reliability: Low–Medium. Thermal: Low. Scalability: Low. Manufacturing: Medium. PCB: High. Debuggability: Medium. Maintainability: Low. Future evolution: Poor. Risk: High.
Candidate B — Fully independent clocks with software timestamp synchronization only
Advantages: Strong fault independence and board replaceability; simple physical boundaries.
Disadvantages: Drift; weaker deterministic cross-board time; timestamp reconciliation required.
Reliability: High. Thermal: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low.
Disadvantages: Drift; weaker deterministic cross-board time; timestamp reconciliation required.
Reliability: High. Thermal: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low.
Candidate C — Independent local clocks plus optional dedicated sync/reference path
PIB and CCB retain local ownership; PMI
SYNC_CLK or time messages align timestamps; HSX/Ethernet references remain local to CCB.Advantages: Independence plus optional synchronization; no safety dependency on cross-board clock; flexible Core revisions.
Disadvantages: Additional sync validation; two clock domains remain to reconcile.
Reliability: High. Thermal: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low.
Disadvantages: Additional sync validation; two clock domains remain to reconcile.
Reliability: High. Thermal: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low.
Preferred topology
Candidate C: independent local clock domains with optional PMI synchronization. PIB safety timing is always local. CCB owns compute, Ethernet and HSX references. Loss of required local clock asserts the associated reset and cannot leave high-power authorization active.
18. Supervisor Architecture
Functional objective
Implement energy/safety authority, source/battery policy, sequencing, telemetry, watchdog, fault logging and PMI management independent of the application Core.
Candidate A — CCB Core controls all power; PIB uses simple combinational protection
Advantages: One firmware domain and simplified communications.
Disadvantages: Violates authority model; Core crash can prevent safe power decisions; impossible restricted boot of incompatible CCB.
Reliability: Low. Thermal: Low. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: Medium. Maintainability: Low. Future evolution: Poor. Risk: Unacceptable.
Disadvantages: Violates authority model; Core crash can prevent safe power decisions; impossible restricted boot of incompatible CCB.
Reliability: Low. Thermal: Low. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: Medium. Maintainability: Low. Future evolution: Poor. Risk: Unacceptable.
Candidate B — One PIB supervisor controller plus independent analog protection
Advantages: Clear authority, manageable complexity, autonomous boot, rich telemetry; hardware handles destructive limits.
Disadvantages: Supervisor is a functional single point for policy; firmware quality and watchdog are critical.
Reliability: High. Thermal: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low–Medium.
Disadvantages: Supervisor is a functional single point for policy; firmware quality and watchdog are critical.
Reliability: High. Thermal: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low–Medium.
Candidate C — Dual redundant PIB supervisors with voting/cross-monitoring
Advantages: Higher fault tolerance and diagnostic coverage.
Disadvantages: Major complexity, synchronization, common-cause analysis, cost and certification burden; no target safety integrity level currently requires it.
Reliability: Potentially very high. Thermal: Low. Scalability: Medium. Manufacturing: High. PCB: High. Debuggability: Low–Medium. Maintainability: Low. Future evolution: Specialized. Risk: High.
Disadvantages: Major complexity, synchronization, common-cause analysis, cost and certification burden; no target safety integrity level currently requires it.
Reliability: Potentially very high. Thermal: Low. Scalability: Medium. Manufacturing: High. PCB: High. Debuggability: Low–Medium. Maintainability: Low. Future evolution: Specialized. Risk: High.
Preferred topology
Candidate B: one dedicated PIB supervisor domain backed by independent analog/hardware protection, independent watchdog, safe-state gates, and nonvolatile critical fault retention. This meets the current generic safety scope without unjustified redundant-controller complexity.
19. Fault Latching Strategy
Functional objective
Ensure serious faults remain safe, recoverable faults can retry within limits, causes survive resets, and no reset automatically reenergizes API/high-power domains.
Candidate A — Firmware-only fault flags
Advantages: Flexible and easy to update.
Disadvantages: Lost on crash/reset; not independent; cannot guarantee immediate high-energy isolation.
Reliability: Low. Thermal: N/A. Scalability: High. Manufacturing: Low. PCB: Low. Debuggability: Medium. Maintainability: High. Future evolution: Good. Risk: Unacceptable.
Disadvantages: Lost on crash/reset; not independent; cannot guarantee immediate high-energy isolation.
Reliability: Low. Thermal: N/A. Scalability: High. Manufacturing: Low. PCB: Low. Debuggability: Medium. Maintainability: High. Future evolution: Good. Risk: Unacceptable.
Candidate B — Hardware latch for every fault
Advantages: Deterministic persistence and safety.
Disadvantages: Excess latches, service complexity, nuisance lockouts; difficult categorization and remote recovery.
Reliability: High. Thermal: Low. Scalability: Medium. Manufacturing: High. PCB: Medium–High. Debuggability: High. Maintainability: Low–Medium. Future evolution: Moderate. Risk: Medium.
Disadvantages: Excess latches, service complexity, nuisance lockouts; difficult categorization and remote recovery.
Reliability: High. Thermal: Low. Scalability: Medium. Manufacturing: High. PCB: Medium–High. Debuggability: High. Maintainability: Low–Medium. Future evolution: Moderate. Risk: Medium.
Candidate C — Tiered fault model with hardware serious-fault latch, bounded recoverable retries, and nonvolatile event log
Advantages: Correct response proportional to severity; serious faults survive controller reset; service diagnosis retained; recoverable loads can self-heal.
Disadvantages: Requires a formal fault taxonomy, clear/reset permissions, and retry counters.
Reliability: High. Thermal: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low.
Disadvantages: Requires a formal fault taxonomy, clear/reset permissions, and retry counters.
Reliability: High. Thermal: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low.
Preferred topology
Candidate C: tiered fault latching. Destructive electrical faults, emergency inhibit, reverse energy, repeated API faults and incompatible power states latch in hardware or hardware-backed state. Recoverable communication/module faults receive bounded retries. All events are logged; clearing never directly reenables high power.
20. Thermal Monitoring Strategy
Functional objective
Detect and control connector, power-path, conversion, Core, API and expansion hotspot temperatures using placement-aware sensors and thermal models.
Candidate A — One ambient/board temperature sensor per board
Advantages: Minimal cost and complexity.
Disadvantages: Poor correlation to local junction/contact hotspots; slow fault detection; cannot distinguish blocks.
Reliability: Low–Medium. Thermal burden: Low. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: Low. Maintainability: Medium. Future evolution: Weak. Risk: High.
Disadvantages: Poor correlation to local junction/contact hotspots; slow fault detection; cannot distinguish blocks.
Reliability: Low–Medium. Thermal burden: Low. Scalability: Low. Manufacturing: Low. PCB: Low. Debuggability: Low. Maintainability: Medium. Future evolution: Weak. Risk: High.
Candidate B — Temperature sensing only inside power devices/modules
Advantages: Direct junction protection when available; no extra placement.
Disadvantages: Component-dependent and unavailable before selection; misses connector/copper/battery/environment hotspots; telemetry may disappear on device fault.
Reliability: Medium. Thermal burden: Low. Scalability: Medium. Manufacturing: Low. PCB: Low. Debuggability: Medium. Maintainability: Medium. Future evolution: Moderate. Risk: High.
Disadvantages: Component-dependent and unavailable before selection; misses connector/copper/battery/environment hotspots; telemetry may disappear on device fault.
Reliability: Medium. Thermal burden: Low. Scalability: Medium. Manufacturing: Low. PCB: Low. Debuggability: Medium. Maintainability: Medium. Future evolution: Moderate. Risk: High.
Candidate C — Distributed board sensors plus device/module telemetry and hardware local thermal trips at critical paths
Advantages: Correlates to input contacts, bus, Core stage, API, CCB hotspot and HSX zone; supports characterization and derating; retains local protection.
Disadvantages: More sensors, routing and calibration; placement must follow thermal simulation/testing.
Reliability: High. Thermal burden: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low–Medium.
Disadvantages: More sensors, routing and calibration; placement must follow thermal simulation/testing.
Reliability: High. Thermal burden: Low. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low–Medium.
Preferred topology
Candidate C: distributed thermal monitoring. Mandatory zones are both USB input paths, protected bus/source-arbitration region, Core 5 V stage, battery path on battery SKUs, API path/connector, CCB Core hotspot, and HSX module zone. Hardware trips protect destructive paths; firmware performs derating and trend analysis.
21. Power Sequencing Architecture
Functional objective
Coordinate source validation, passive identity, restricted discovery, Core startup, local POLs, PMI heartbeat, module discovery, full-power grants, graceful shutdown and emergency isolation.
Candidate A — Fixed analog delay chain
Advantages: Deterministic and firmware-independent; simple for a fixed product.
Disadvantages: Cannot adapt to modules, source contracts, revisions or fault history; delay tolerances; poor diagnostics.
Reliability: Medium. Thermal: N/A. Scalability: Low. Manufacturing: Low–Medium. PCB: Medium. Debuggability: Low. Maintainability: Low. Future evolution: Poor. Risk: High.
Disadvantages: Cannot adapt to modules, source contracts, revisions or fault history; delay tolerances; poor diagnostics.
Reliability: Medium. Thermal: N/A. Scalability: Low. Manufacturing: Low–Medium. PCB: Medium. Debuggability: Low. Maintainability: Low. Future evolution: Poor. Risk: High.
Candidate B — Firmware-only sequencer using GPIO enables and sampled PG
Advantages: Flexible, easy policy updates, rich logs.
Disadvantages: Unsafe during reset/crash; startup dependencies; may drive rails before firmware validates hardware; insufficient independent timing.
Reliability: Low–Medium. Thermal: N/A. Scalability: High. Manufacturing: Low. PCB: Low. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: High.
Disadvantages: Unsafe during reset/crash; startup dependencies; may drive rails before firmware validates hardware; insufficient independent timing.
Reliability: Low–Medium. Thermal: N/A. Scalability: High. Manufacturing: Low. PCB: Low. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: High.
Candidate C — Hybrid hardware-enforced state machine with supervisor policy
Hardware establishes safe defaults, source qualification, reset gating, timeouts and emergency removal; the PIB supervisor advances states, validates descriptors/budgets and logs events; CCB sequences its local POLs within the granted Core state.
Advantages: Safety plus flexibility; supports versioned modules and degraded modes; clear timeout/fault responses; scalable.
Disadvantages: Requires formal state-machine specification and thorough transition testing.
Reliability: High. Thermal: N/A. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low–Medium.
Disadvantages: Requires formal state-machine specification and thorough transition testing.
Reliability: High. Thermal: N/A. Scalability: High. Manufacturing: Medium. PCB: Medium. Debuggability: High. Maintainability: High. Future evolution: Strong. Risk: Low–Medium.
Preferred topology
Candidate C: hybrid hardware-enforced, supervisor-directed sequencing. The canonical order is AON → source validation → passive ID → discovery → compatibility/budget → Core 5 V → CCB POL/clock valid → Core release → PMI heartbeat → module discovery → approved full rails. Emergency inhibit bypasses graceful sequencing; brownout follows load-shed and bounded shutdown.
22. Platform Topology Summary
Table
| Functional block | Selected topology | Key architectural reason |
|---|---|---|
| USB-C Input Protection | Independent active hot-swap/e-fuse path per port with back-to-back isolation | Lowest-loss independent protection, controlled inrush, no cross-feed |
| Source Arbitration | Supervisor-commanded break-before-make with hardware interlock | Explicit no-aggregation and policy-aware handover |
| Protected System Bus | Hybrid direct protected 20 V pass-through plus conversion for restricted/battery modes | High normal efficiency without losing degraded-mode support |
| Battery Path | Controlled bidirectional buck-boost with precharge and hard isolation | Supports charging, UPS and bounded peak assist across a qualified pack class |
| AON Supply | Efficient high-voltage preregulator plus segmented quiet/local rails | Low standby loss and fault-isolated safety/discovery domains |
| Core 5 V | Single-phase synchronous buck for Standard Tier, migration path to multiphase | Appropriate for 25 W Core ceiling with lower complexity |
| Local POL | Hierarchical mixed switching, quiet post-regulation and switched domains | Balances efficiency, noise, sequencing and compute evolution |
| API Path | Back-to-back disconnect, limited precharge, current/thermal trip and discharge | Safe 5 A continuous/8 A transient bounded output |
| AUX Rails | Independent dedicated 12 V and 5 V buck stages | Fault independence and straightforward service behavior |
| LSX Power | Central full rails plus per-port load switches and separate discovery rail | Discovery-first policy and low-power fault containment |
| HSX Power | Protected high-current load switch from CCB 5 V plus discovery/reset/clock gating | Low loss, strict sequencing, module isolation |
| Current Measurement | Hybrid high-side bidirectional shunts plus independent fast trip paths | Accurate allocation with low-loss destructive-fault response |
| Voltage Monitoring | Hardware window/trip plus ADC telemetry | Fast protection and rich diagnostics |
| Protection | Layered selectively coordinated boundaries | Contains faults without excessive duplication |
| Reset | Hierarchical hardware-gated reset tree | Safe startup/brownout and clear PIB/CCB authority |
| Clock | Independent local clocks with optional PMI synchronization | Fault independence and upgradeability |
| Supervisor | Dedicated PIB supervisor backed by independent hardware protection/watchdog | Energy/safety authority independent of application Core |
| Fault Latching | Tiered hardware serious-fault latch, bounded retries, nonvolatile logs | Safe persistence without needless service lockout |
| Thermal Monitoring | Distributed board sensing plus device telemetry and local trips | Correlation to real hotspots and controlled derating |
| Power Sequencing | Hybrid hardware-enforced, supervisor-directed state machine | Safe defaults with version/module flexibility |
23. Cross-topology consistency rules
- No selected topology permits simultaneous USB-C source connection for aggregation.
- AON and hardware protection do not depend on the CCB Core.
- The Heavy state remains limited by the 90 W continuous envelope; topology capacity does not grant workload permission.
- The Absolute Peak path remains disabled until a qualified battery class and transient thermal/SOA analysis exist.
- All full expansion rails require passive ID, restricted discovery, descriptor acceptance, budget reservation, and power-good validation.
- Every high-energy path has a hardware disconnect independent of telemetry firmware.
- Current/voltage/thermal telemetry never substitutes for local destructive-fault trips.
- Core-specific low-voltage rails remain local to the CCB.
- Internal module connectors remain cold-mate in v1.0.
- API remains non-regenerative; reverse energy is a fault.
- Reserved interface pins remain unused until controlled revision.
- Reset, enable, PG, clock and fault states default to high-power OFF.
24. Engineering validation required before component selection
Phase 4 shall not begin until the following topology inputs are approved or explicitly bounded:
- Qualified battery pack class, or removal/deferral of battery-assist Absolute Peak.
- Final protected-bus normal and transient voltage window.
- Heavy-state continuous duty and margin resolution.
- Source-transfer ride-through and graceful-shutdown hold-up requirements.
- Exact field ESD/EFT/surge and environmental classes.
- API pulse waveform, cable assumptions, permitted capacitance/inrush, and thermal repetition.
- CCB compute-tier rail sequence, peak load step, clock classes and local POL requirements.
- HSX supported protocol subset and channel/clock constraints.
- Required measurement accuracy, bandwidth, calibration and telemetry update rates.
- Hardware trip thresholds, response times, retry counts and fault-clear authority.
- Thermal sensor zones and target derating curves.
- Connector-family feasibility, contact derating and 40 mm stack solution.
25. Phase 3B compliance checklist
Table
| Requirement | Coverage | Status |
|---|---|---|
| No IC/MPN selection | Scope and all recommendations are topology-only | Complete |
| No schematic, BOM, footprints or layout | No EDA design mutation performed | Complete |
| USB-C input protection study | Section 2 | Complete |
| Source arbitration | Section 3 | Complete |
| Protected system bus | Section 4 | Complete |
| Battery path | Section 5 | Complete |
| AON supply | Section 6 | Complete |
| Core 5 V | Section 7 | Complete |
| Local POL | Section 8 | Complete |
| API path | Section 9 | Complete |
| AUX rail generation | Section 10 | Complete |
| LSX power | Section 11 | Complete |
| HSX power | Section 12 | Complete |
| Current measurement | Section 13 | Complete |
| Voltage monitoring | Section 14 | Complete |
| Protection strategy | Section 15 | Complete |
| Reset generation | Section 16 | Complete |
| Clock distribution | Section 17 | Complete |
| Supervisor architecture | Section 18 | Complete |
| Fault latching | Section 19 | Complete |
| Thermal monitoring | Section 20 | Complete |
| Power sequencing | Section 21 | Complete |
| Functional objective for every block | Sections 2–21 | Complete |
| Candidate A/B/C where appropriate | Sections 2–21 | Complete |
| Advantages/disadvantages and formal evaluation dimensions | Each candidate study | Complete |
| One preferred topology and reasoning per block | Sections 2–21 | Complete |
| Complete Platform Topology Summary | Section 22 | Complete |
| Future component-selection reference | Sections 22–24 | Complete, pending review gates |
26. Review disposition
Phase 3B Functional Topology Selection status: COMPLETE FOR LEAD-ARCHITECT REVIEW.
This document is the topology reference for future component selection. It does not authorize Phase 4 until the review items in Section 24 are closed or formally accepted.
This document is the topology reference for future component selection. It does not authorize Phase 4 until the review items in Section 24 are closed or formally accepted.
NEXUS-S3 Functional Topology Selection v1.0
1. Evaluation method
2. USB-C Input Protection and Power Path
Functional objective
Candidate A — Passive fuse/diode front end plus downstream switch
Candidate B — Per-port active hot-swap/e-fuse topology with back-to-back isolation
Candidate C — Central shared protection after minimally isolated ports
Preferred topology
3. Source Arbitration
Functional objective
Candidate A — Fixed-priority diode-OR arbitration
Candidate B — Active ideal-diode OR with autonomous highest/first-valid selection
Candidate C — Supervisor-commanded break-before-make arbitration with hardware interlock
Preferred topology
4. Protected System Bus
Functional objective
Candidate A — Unregulated selected-source bus
Candidate B — Central regulated non-isolated buck-boost bus
Candidate C — Hybrid bus: direct protected 20 V pass-through with conversion only for non-20 V or battery modes
Preferred topology
5. Battery Path
Functional objective
Candidate A — Pack directly ORed to the system bus with separate charger
Candidate B — Separate unidirectional charger plus controlled boost discharge path
Candidate C — Single controlled bidirectional buck-boost battery power path with precharge and hard isolation
Preferred topology
6. AON Supply Architecture
Functional objective
Candidate A — Single linear regulator from bus
Candidate B — Single always-on high-voltage buck directly to one logic rail
Candidate C — Two-stage AON: efficient high-voltage preregulator plus quiet/segmented low-voltage rails
Preferred topology
7. Core 5 V Generation
Functional objective
Candidate A — Single-phase synchronous buck
Candidate B — Interleaved multiphase synchronous buck
Candidate C — Distributed two-stage Core input conversion
Preferred topology
8. Local POL Strategy
Functional objective
Candidate A — One centralized multi-output conversion cluster
Candidate B — Fully distributed independent converters at every load
Candidate C — Hierarchical mixed POL: efficient switching for power rails, quiet post-regulation/filtering for sensitive rails, switched load domains
Preferred topology
9. API Power Path
Functional objective
Candidate A — Single high-side switch with current limit
Candidate B — Back-to-back disconnect with separate precharge and shunt-based monitoring
Candidate C — Fully regulated isolated or non-isolated API converter
Preferred topology
10. AUX Rail Generation
Functional objective
Candidate A — Separate dedicated buck converter for each rail
Candidate B — 12 V primary buck with cascaded 5 V buck
Candidate C — Single multi-output coupled conversion stage
Preferred topology
11. LSX Power Distribution
Functional objective
Candidate A — Permanently powered shared LSX rails
Candidate B — One shared full rail with per-connector switches
Candidate C — Dedicated conversion per LSX port
Preferred topology
12. HSX Power Distribution
Functional objective
Candidate A — Direct connection to CCB 5 V with module-controlled startup
Candidate B — High-current load switch/e-fuse from CCB 5 V with discovery branch
Candidate C — Dedicated HSX 5 V converter from optional PPI 12 V or another intermediate rail
Preferred topology
13. Current Measurement Strategy
Functional objective
Candidate A — High-side shunt measurement everywhere
Candidate B — Low-side shunt measurement everywhere
Candidate C — Hybrid sensing: high-side precision shunts for allocation, fast lossless/low-loss protection sensing where necessary, indirect telemetry for minor rails
Preferred topology
14. Voltage Monitoring Strategy
Functional objective
Candidate A — Supervisor ADC-only monitoring
Candidate B — Dedicated hardware comparators/supervisors only
Candidate C — Dual-path monitoring: hardware window/trip thresholds plus ADC telemetry
Preferred topology
15. Protection Strategy
Functional objective
Candidate A — Centralized protection at source and bus only
Candidate B — Fully duplicated protection at every conversion and load
Candidate C — Layered selective coordination
Preferred topology
16. Reset Generation
Functional objective
Candidate A — RC power-on resets with firmware-managed downstream reset
Candidate B — Dedicated voltage supervisor per critical rail, wired reset tree
Candidate C — Hierarchical reset architecture: hardware supervisors and reset gate, sequencer-controlled distribution, firmware-visible causes
Preferred topology
17. Clock Distribution Strategy
Functional objective
Candidate A — One shared master clock distributed across both boards
Candidate B — Fully independent clocks with software timestamp synchronization only
Candidate C — Independent local clocks plus optional dedicated sync/reference path
Preferred topology
18. Supervisor Architecture
Functional objective
Candidate A — CCB Core controls all power; PIB uses simple combinational protection
Candidate B — One PIB supervisor controller plus independent analog protection
Candidate C — Dual redundant PIB supervisors with voting/cross-monitoring
Preferred topology
19. Fault Latching Strategy
Functional objective
Candidate A — Firmware-only fault flags
Candidate B — Hardware latch for every fault
Candidate C — Tiered fault model with hardware serious-fault latch, bounded recoverable retries, and nonvolatile event log
Preferred topology
20. Thermal Monitoring Strategy
Functional objective
Candidate A — One ambient/board temperature sensor per board
Candidate B — Temperature sensing only inside power devices/modules
Candidate C — Distributed board sensors plus device/module telemetry and hardware local thermal trips at critical paths
Preferred topology
21. Power Sequencing Architecture
Functional objective
Candidate A — Fixed analog delay chain
Candidate B — Firmware-only sequencer using GPIO enables and sampled PG
Candidate C — Hybrid hardware-enforced state machine with supervisor policy
Preferred topology
22. Platform Topology Summary
23. Cross-topology consistency rules
24. Engineering validation required before component selection
25. Phase 3B compliance checklist
26. Review disposition
