USB-C Temperature and Humidity Sensor Node

flux

0:00

Work completed
  • Stackup set to Standard 4 Layer (F.Cu, In1.Cu, In2.Cu, B.Cu)
  • Plane layers defined: In1.Cu as reference, In2.Cu as power
  • Board outline extents determined and PCB size updated with keepouts
  • PCIe/CXL lane-to-net mappings annotated via “LaneMapAnnotations”
  • Four mounting holes placed at corners with 5 mm edge clearance:
  • Keepouts of 5 mm around mounting holes applied on all copper layers
Tasks remaining
  • Run ERC and DRC reviews and resolve any violations
  • Export deliverables:
    • IPC-D-356 netlist
    • BOM with LCSC MPNs
    • Routing strategy document
Unachievable tasks
  • Tag PCIe Gen5 x16/CXL nets as differential pairs
  • Set per-net differential-impedance, spacing, length-matching, and skew properties
Success criteria status
  • 4-layer stackup and planes: ✅
  • PCIe/CXL differential-pair rules: ❌ (mapping only, no impedance rules)
  • Mounting holes and keepouts: ✅
  • ERC/DRC checks: ❌
  • Deliverable exports: ❌
Next step Run the PCB ERC and DRC checks, review any violations, and then proceed to resolve them before exporting the netlist, BOM, and routing strategy.
85 days
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PCIe Gen5 x16 CXL Type 3 Carrier with Switchtec PAX Gen5 NTB, Intel Agilex 7 FPGA, COM-HPC Client A, and Robust 12 V Power/HS Routing (IPC-D-356, LCSC BOM, Routing Strategy)

Properties

Lane0_TX={net for J1 TXP0}/{net for J1 TXN0};Lane0_RX={net for J1 RXP0}/{net for J1 RXN0};Lane1_TX={net for J1 TXP1}/{net for J1 TXN1};Lane1_RX={net for J1 RXP1}/{net for J1 RXN1};Lane2_TX={net for J1 TXP2}/{net for J1 TXN2};Lane2_RX={net for J1 RXP2}/{net for J1 RXN2};Lane3_TX={net for J1 TXP3}/{net for J1 TXN3};Lane3_RX={net for J1 RXP3}/{net for J1 RXN3};Lane4_TX={net for J1 TXP4}/{net for J1 TXN4};Lane4_RX={net for J1 RXP4}/{net for J1 RXN4};Lane5_TX={net for J1 TXP5}/{net for J1 TXN5};Lane5_RX={net for J1 RXP5}/{net for J1 RXN5};Lane6_TX={net for J1 TXP6}/{net for J1 TXN6};Lane6_RX={net for J1 RXP6}/{net for J1 RXN6};Lane7_TX={net for J1 TXP7}/{net for J1 TXN7};Lane7_RX={net for J1 RXP7}/{net for J1 RXN7}

PCIe Gen5 x16 CXL Type 3 carrier card using a Switchtec PAX Gen5 fabric switch to fan out to an Intel Agilex 7 FPGA and a COM-HPC Client Size A module, with 12V input and on-board 5V and 3.3V regulation.

Top.Cu, Bottom.Cu

In1.Cu, In2.Cu

12

V

CXL Type 3

Mains

Computing / Data Center

PCIe

Standard 4 Layer (F.Cu, In1.Cu, In2.Cu, B.Cu)

In1.Cu: Reference, In2.Cu: Power

PCIe 5.0

5mm clearance around Hole1, Hole2, Hole3, Hole4, Hole5, Hole6, Hole7, Hole8 mounting hole footprints on all copper layers

Diagram



  
    
  
  
    
  
















PCIe Gen5 x16 Edge Connector
Switchtec PAX Gen5 Fabric Switch
Intel Agilex 7 FPGA
COM-HPC Client Size A Connector
12V->5V Regulator
12V->3.3V Regulator

Pricing & Availability

Distributor

Qty 1

Arrow

$1,455.98–$1,460.24

Digi-Key

$27.14–$44.61

LCSC

$494.56–$494.64

Mouser

$1,449.05

TME

$0.37

Verical

$10.81–$11.33

Controls