HV Pulse Power Design

flux

Expanded the schematic from 92 to 172 components with:
  • Six-cell graphene/EDLC supercapacitor interface
  • External 4S LiFePO₄/BMS interface
  • Isolated charger and bidirectional converter interfaces
  • Channel 4 auxiliary self-power path with startup-power ORing
  • ESP32-WROOM-32E and three ADS1115 telemetry ADCs
  • Independent hardware charger/inverter shutdown
  • Protected 40 A-class external inverter interface
  • Separate HV GND and low-voltage LV_GND
Floating comparator and control-power errors were corrected; floating-pin and missing-power checks are now clean.
Open items
  • Exact isolated charger, bidirectional converter, BMS, and active supercapacitor-balancer modules require measured capture voltage, source impedance, and sustainable power.
  • The new components still need PCB placement; routing has not started.
  • The inverter remains an external certified module rather than onboard mains circuitry.
Project files
Next steps
  1. Re-size and place all 172 footprints by power domain.
  2. Select the external converter and BMS modules from measured source data.
  3. Apply HV/high-current layout rules and isolation boundaries.
  4. Review placement before routing.
Place expanded PCB
Select power modules
Set high-voltage rules
Review safety design
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Block Diagram
Text
CH1 floating HV IN -> fast bridge -> CAP1 + bleeder + divider/clamp + TP -> isolated/provisional transfer connector --X--+
CH2 floating HV IN -> fast bridge -> CAP2 + bleeder + divider/clamp + TP -> isolated/provisional transfer connector --X--+--> protected common HV bus -> future isolated DC/DC connector
CH3 floating HV IN -> fast bridge -> CAP3 + bleeder + divider/clamp + TP -> isolated/provisional transfer connector --X--+
CH4 floating HV IN -> fast bridge -> CAP4 + bleeder + divider/clamp + TP -> isolated/provisional transfer connector --X--+

AUX 12 V control input -> control protection/decoupling -> hardware shutdown chain
E-stop/interlock + bus OVP + channel OVP inhibits -> fail-safe latch/manual reset -> DRIVER_KILL / TRANSFER_ENABLE
Binding architecture decisions
  • Four independent floating two-terminal sources; no raw-AC paralleling.
  • Each source is full-wave rectified and captured locally.
  • First revision is a characterization platform, not a claimed production converter.
  • Unknown source impedance prevents responsible current-transfer sizing. Transfer paths are therefore connectorized and disabled/provisional; no direct capacitor dumping.
  • Common bus is protected, sensed, discharged, and exposed only to a future isolated regulated DC/DC stage.
  • Hardware shutdown defaults OFF and is independent of firmware.
  • LEDs, if fitted, are low-voltage control-side status/event indicators only.
Reference classification
  • HV capture/rectification: none found; library-sourced from scratch.
  • Protected common bus: none found; library-sourced from scratch.
  • Hardware interlock/OVP: none found; library-sourced from scratch.
  • Measurement/test interfaces: none found; library-sourced from scratch.

  • Binding architecture decisions

  • Reference classification

Dipole Transformer Generator

Dipole Transformer Generator thumbnail
Four-channel high-voltage transient capture and characterization platform with individually rectified inputs, protected DC bus, controlled energy transfer, and independent hardware shutdown.

Properties

Properties describe core aspects of the project.

Pricing & Availability

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Arrow

$37.39–$57.23

Digi-Key

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HQonline

$3.42–$3.51

LCSC

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Mouser

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TME

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Verical

$39.17–$49.16

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