HV Pulse Power Design

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Expanded the schematic from 92 to 172 components with:
  • Six-cell graphene/EDLC supercapacitor interface
  • External 4S LiFePO₄/BMS interface
  • Isolated charger and bidirectional converter interfaces
  • Channel 4 auxiliary self-power path with startup-power ORing
  • ESP32-WROOM-32E and three ADS1115 telemetry ADCs
  • Independent hardware charger/inverter shutdown
  • Protected 40 A-class external inverter interface
  • Separate HV GND and low-voltage LV_GND
Floating comparator and control-power errors were corrected; floating-pin and missing-power checks are now clean.
Open items
  • Exact isolated charger, bidirectional converter, BMS, and active supercapacitor-balancer modules require measured capture voltage, source impedance, and sustainable power.
  • The new components still need PCB placement; routing has not started.
  • The inverter remains an external certified module rather than onboard mains circuitry.
Project files
Next steps
  1. Re-size and place all 172 footprints by power domain.
  2. Select the external converter and BMS modules from measured source data.
  3. Apply HV/high-current layout rules and isolation boundaries.
  4. Review placement before routing.
Place expanded PCB
Select power modules
Set high-voltage rules
Review safety design
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Files

Schematic

Layout

Preview

Board Operation Guide
What this board is
This is a four-channel high-voltage transient capture and characterization board. It accepts four independent plate-group signals, rectifies each channel separately, stores each channel's captured transient energy locally, measures the channel voltage, and combines the channels onto a fused protected DC bus.
This revision now includes interfaces and supervision for the later hybrid-power stages: a six-cell supercapacitor bank, external 4S LiFePO4/BMS, isolated charger module, bidirectional supercap/battery converter module, ESP32 telemetry, Channel 4 auxiliary power, and an external 300 W pure-sine inverter. The high-power converters and inverter remain external certified modules because their exact ratings depend on measured capture power and final module selection.
Energy flow
  1. Plate groups connect to J1 through J4.
  2. BR1 through BR4 independently rectify the four AC/transient inputs.
  3. C1 through C4 are local channel capture capacitors.
  4. High-value resistor networks bleed the capacitors and divide the captured voltage to safe sense levels.
  5. D1 through D4 provide channel isolation while transferring captured energy toward the common bus.
  6. F1 protects the common DC bus.
  7. LM339 comparator circuits monitor the channel and bus sense voltages.
  8. CD4013 U3 latches the original capture-side fault so shutdown remains asserted until SW1 RESET is pressed.
  9. A six-cell supercapacitor interface buffers short power bursts while monitoring the cell taps.
  10. External isolated charger and bidirectional converter interfaces move energy under current limit into the 4S LiFePO4 storage bus.
  11. ESP32 U7 and three ADS1115 ADCs provide telemetry and command requests; hardware comparator U4/U5 and optocoupler U6 remain authoritative.
  12. The protected 12.8 V battery bus feeds an external certified inverter interface for the laptop load.
External connections

Table

ConnectorFunction
J1Plate group 1, terminals A/B
J2Plate group 2, terminals A/B
J3Plate group 3, terminals A/B
J4Plate group 4, terminals A/B
J5Channel 1 sense output and GND
J6Channel 2 sense output and GND
J7Channel 3 sense output and GND
J8Channel 4 sense output and GND
J9Protected common DC bus and GND
J10External 5 V control power and GND
J11Latched fault output and GND
J12Transfer-enable output and GND
Indicators and controls
  • LED1 — FAULT: illuminates when the hardware fault latch is active.
  • LED2 — TRANSFER: indicates the transfer-enable state.
  • SW1 — RESET: manually clears the hardware shutdown latch after the source is safe.
  • F1 — DC BUS FUSE: protects the common bus from excessive current.
Later-stage interfaces
  • Six external 2.7 V supercapacitor cells, approximately 300 F each, connect through the supercapacitor bank and cell-tap interfaces.
  • A certified external 4S LiFePO4 BMS connects to the battery/BMS interface.
  • A verified isolated capture-to-14.6 V charger module connects to the charger interface.
  • A verified 300 W bidirectional supercapacitor/battery DC/DC module connects to its command and telemetry header.
  • A certified external 300 W pure-sine inverter connects to the fused battery bus and remote-enable/status interface.
Intended test sequence
  1. Power only the 5 V control section through J10 and confirm no unexpected heating.
  2. Verify the reference and comparator thresholds before applying high voltage.
  3. Test one plate channel at low energy, using its sense connector and test points.
  4. Calculate captured energy from the measured capacitor voltage change: E = 0.5 C (Vhigh^2 - Vlow^2).
  5. Repeat for all four channels independently.
  6. Connect the common bus to a current-limited resistive or electronic load through J9.
  7. Confirm fuse, fault latch, reset, and transfer-enable behavior.
  8. Select and connect the external isolated charger only after measured joules per event, voltage range, and sustainable event rate are known.
  9. Validate the supercapacitor bank with low-capacitance test devices before installing large cells.
  10. Validate the BMS, precharge, contactor, bidirectional module, and inverter independently before combining the system.
Safety limits
  • Treat J1 through J9 and the capture capacitors as hazardous high-voltage nodes.
  • Do not short a charged capture capacitor to the common bus.
  • Use a regulated current-limited conversion stage for energy transfer.
  • Verify capacitor discharge with a meter before touching the board.
  • Use insulated probes, barriers, bleeders, interlocks, and an enclosed test fixture.

  • What this board is

  • Energy flow

  • External connections

  • Indicators and controls

  • Later-stage interfaces

  • Intended test sequence

  • Safety limits