555 Timer Circuit Design

Right now, none of those terminals are connected to anything yet.
Current terminal mapping

Table


DesignatorLinkCurrent connection statePin Number
AAUnconnected1
BBUnconnected2
CCUnconnected5
DDUnconnected6
EEUnconnected8
FFUnconnected9
GGUnconnected12
HHUnconnected13
JJUnconnected3
KKUnconnected4
LLUnconnected10
MMUnconnected11
Net status

Table


Result
No nets have been defined yet
So at the moment, A, B, C, D, E, F, G, H, J, K, L, and M are just placeholder terminals in the part symbol, not wired together.
If you want, I can also map these terminals to the CD4093BM96 package pinout meaning.
ok draw the schematic
You want the placeholder part schematic replaced with a compact 5 V TLC555CDR astable oscillator at about 1 kHz and near-50% duty cycle.
  • The plan is ready to execute.
  • It replaces the current terminal-only content, adds the oscillator and 0603 support parts, maps power/output terminals, and verifies the design target.
Click Start on the plan bar to run it.
Add exact values
Include decoupling cap
Check oscillator parts
D
C
VDD
J
E
M
Vss
K
G
F
B
A
L
H

To get started, talk to Flux or create a New Document.

Documents

    Documents are markdown text files which describe project goals, capture details, or even simulation outputs.

    Assets

    SOIC-14_3.9x8.7mm_P1.27mm.png

    SOIC-14_3.9x8.7mm_P1.27mm.png

    SOIC-14_3.9x8.7mm_P1.27mmThumbnail
    kicad_mod

    SOIC-14_3.9x8.7mm_P1.27mm.kicad_mod

    F-V5Footprint
    SOIC-14_3.9x8.7mm_P1.27mm

    SOIC-14_3.9x8.7mm_P1.27mm

    defaultDefault
    step

    SOIC-14_3.9x8.7mm_P1.27mm.step

    3D3D Model

    CD4093BM96

    CD4093BM96 thumbnail
    NAND Gate IC 4 Channel Schmitt Trigger 14-SOIC #CommonPartsLibrary #IntegratedCircuit #Logic #Gate #Inverter

    Properties

    Integrated Circuit

    Texas Instruments

    CD4093BM96

    U

    Pricing & Availability

    Distributor

    Qty 1

    Controls