Project Overview and Analysis
Worked for 1 min 14 sec
The remaining airwires are caused by blocked U1/J3 escape routing, so I’m going to compact the placement: logic header near U1, LVDS headers/termination on the opposite side, then remove stale routing and reroute.
Worked for 3 mins 22 sec
Placement is now adjusted for U1 escape clearance with J3 on the logic side and the LVDS components on the opposite side; I’m clearing stale routing again and running the router.
Worked for 4 mins 22 sec
Routing completed after the placement rework; I’m checking whether the LVDS route improved and whether U1/J3 airwires remain.
Worked for 6 mins 12 sec
Reworked placement and routing: J3 is now on the logic side of U1, J1/J2/RTERM are on the LVDS side, stale routing was cleared, U1 escape rules were relaxed for fine-pitch access, and the board was re-routed successfully. Verification now reports no open/error/warning airwire or routing checks for the reviewed DRC set, and
LVDS_P/LVDS_N both have routed trace segments present.Estimated time saved vs. manual EDA workflow: ~2–4 hours.
Open items:
- The schematic still connects
J1,J2,U1, andRTERMto the same LVDS pair, so it is physically improved but not a pure single-receiver point-to-point topology unless one header is removed or isolated. - Final 100 Ω impedance still needs fab stackup confirmation.
Suggested next steps:
- Run a focused signal-integrity review on the updated LVDS route.
- Decide whether J1/J2 are both required or whether one should be removed to eliminate stubs.
- Confirm trace geometry with the board manufacturer’s impedance calculator.
Review, remove stub
Run SI review
Remove one header
Confirm impedance
Export check files
