Project Overview and Analysis

flux

Routing completed after the placement rework; I’m checking whether the LVDS route improved and whether U1/J3 airwires remain.

flux

Reworked placement and routing: J3 is now on the logic side of U1, J1/J2/RTERM are on the LVDS side, stale routing was cleared, U1 escape rules were relaxed for fine-pitch access, and the board was re-routed successfully. Verification now reports no open/error/warning airwire or routing checks for the reviewed DRC set, and LVDS_P/LVDS_N both have routed trace segments present.
Estimated time saved vs. manual EDA workflow: ~2–4 hours.
Open items:
  • The schematic still connects J1, J2, U1, and RTERM to the same LVDS pair, so it is physically improved but not a pure single-receiver point-to-point topology unless one header is removed or isolated.
  • Final 100 Ω impedance still needs fab stackup confirmation.
Suggested next steps:
  1. Run a focused signal-integrity review on the updated LVDS route.
  2. Decide whether J1/J2 are both required or whether one should be removed to eliminate stubs.
  3. Confirm trace geometry with the board manufacturer’s impedance calculator.
Review, remove stub
Run SI review
Remove one header
Confirm impedance
Export check files
J1 4 - J2 4
J1 3 - J2 3
U1 ROUT1 - J3 4
U1 DIN1 - J3 3
J1 3 - J2 3
U1 VDD - J3 1
U1 VDD - J3 1
U1 VDD - J3 1
U1 ROUT1 - J3 4
J1 3 - J2 3
J1 4 - J2 4
U1 VDD - J3 1
U1 VDD - J3 1
U1 VDD - J3 1
J1 3 - J2 3
U1 VDD - J3 1
J1 4 - J2 4
J1 4 - J2 4
U1 DIN1 - J3 3
U1 VDD - J3 1
J1 4 - J2 4
J1 3 - J2 3
U1 GND - J3 2
C2
Capacitance
1uF
J3
U1 GND - J3 2
J1
J2
C1
Capacitance
100nF
GND
U1 GND - J3 2
U1 GND - J3 2
RTERM
Resistance
100Ω
U1 GND - J3 2
GND
U1 GND - J3 2
U1

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Board Bring-Up Plan — LVDS Differential PCB
Prerequisites
  • Equipment: current-limited 3.3 V supply, multimeter, oscilloscope with differential probe if available, signal generator or 3.3 V logic source.
  • Safety: power the board from VCC_LVDS at 3.3 V only; DS90LV049 recommended operating supply is 3.0–3.6 V.
1. Visual Inspection
  • Verify U1 DS90LV049TMTX orientation and solder joints.
  • Verify C1 100 nF and C2 1 uF are populated near U1.
  • Verify RTERM is 100 Ω across LVDS_P and LVDS_N.
  • Verify headers J1, J2, and J3 match the documented pinout.
2. Power Rail Verification

Table

RailSourceExpected VoltageMeasure AtCurrent LimitPass Criteria
VCC_LVDSJ3:1 or J1/J2:13.3 VU1:VDD, C1:P1, C2:P1100 mA initial3.0–3.6 V, no excessive current
GNDJ3:2, J1/J2:20 VU1:GND, C1:P2, C2:P2—Continuity to all GND pins
Procedure:
  1. With power off, measure resistance from VCC_LVDS to GND; confirm no short.
  2. Apply 3.3 V with a 100 mA current limit.
  3. Measure U1:VDD to U1:GND.
  4. Check C1/C2 supply pins for the same voltage.
3. Critical Signal Verification

Table

SignalNetExpected StateMeasure AtNotes
EnableVCC_LVDS via U1:ENHighU1:ENEnables outputs
Active-low enableGND via U1:~{EN}LowU1:~{EN}Enables outputs
Logic inputLOGIC_DIN13.3 V logicJ3:3, U1:DIN1Drives LVDS pair
Logic outputLOGIC_ROUT13.3 V logicJ3:4, U1:ROUT1Receiver monitor output
LVDS positiveLVDS_PLVDS differentialJ1:3, J2:3, RTERM:P1100 Ω differential pair
LVDS negativeLVDS_NLVDS differentialJ1:4, J2:4, RTERM:P2100 Ω differential pair
4. Connector and Interface Tests

Table

ConnectorPins to VerifyTest Method
J1 LVDS header1 VCC_LVDS, 2 GND, 3 LVDS_P, 4 LVDS_NContinuity to nets
J2 LVDS header1 VCC_LVDS, 2 GND, 3 LVDS_P, 4 LVDS_NContinuity to nets
J3 logic header1 VCC_LVDS, 2 GND, 3 LOGIC_DIN1, 4 LOGIC_ROUT1, 5 EN, 6 ~EN tied lowContinuity and logic-level measurement
5. Functional Validation

Table

TestInputExpected OutputPass Criteria
Driver pathToggle J3:3 (LOGIC_DIN1)Differential activity on LVDS_P/LVDS_NDifferential waveform visible across RTERM
Receiver monitorDifferential activity on LVDS_P/LVDS_NJ3:4 (LOGIC_ROUT1) togglesLogic output follows receiver state
TerminationMeasure across LVDS_P/LVDS_N unpowered~100 Ω95–105 Ω for 1% resistor
Pass/Fail Summary

Table

SectionResultNotes
Visual Inspection[ ] Pass / [ ] Fail
Power Rails[ ] Pass / [ ] Fail
Connector Pinout[ ] Pass / [ ] Fail
LVDS Functional Test[ ] Pass / [ ] Fail
Board Status: [ ] Ready for layout/routing update / [ ] Requires schematic rework

  • Prerequisites

  • 1. Visual Inspection

  • 2. Power Rail Verification

  • 3. Critical Signal Verification

  • 4. Connector and Interface Tests

  • 5. Functional Validation

  • Pass/Fail Summary

Documents

  • Board Bring-Up Plan — LVDS Differential PCB

  • J3 High-Level Block Diagram

Assets

No assets added.

LVDS Differential PCB

LVDS Differential PCB thumbnail
4-layer controlled-impedance PCB template for RF/LVDS differential routing with 100 Ω differential pair design rules.

Properties

PCB material FR-4; target board thickness 0.062 in / 62 mil / 1.57 mm. Current Flux Standard 4 Layer stackup totals 1.30 mm, so confirm final fab stackup with manufacturer before impedance signoff.

Pricing & Availability

Distributor

Qty 1

Arrow

$2.85–$3.13

LCSC

$3.45

Mouser

$5.02

Verical

$3.06–$7.71

Controls