Project Overview and Analysis

flux

Routing completed after the placement rework; I’m checking whether the LVDS route improved and whether U1/J3 airwires remain.

flux

Reworked placement and routing: J3 is now on the logic side of U1, J1/J2/RTERM are on the LVDS side, stale routing was cleared, U1 escape rules were relaxed for fine-pitch access, and the board was re-routed successfully. Verification now reports no open/error/warning airwire or routing checks for the reviewed DRC set, and LVDS_P/LVDS_N both have routed trace segments present.
Estimated time saved vs. manual EDA workflow: ~2–4 hours.
Open items:
  • The schematic still connects J1, J2, U1, and RTERM to the same LVDS pair, so it is physically improved but not a pure single-receiver point-to-point topology unless one header is removed or isolated.
  • Final 100 Ω impedance still needs fab stackup confirmation.
Suggested next steps:
  1. Run a focused signal-integrity review on the updated LVDS route.
  2. Decide whether J1/J2 are both required or whether one should be removed to eliminate stubs.
  3. Confirm trace geometry with the board manufacturer’s impedance calculator.
Review, remove stub
Run SI review
Remove one header
Confirm impedance
Export check files
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LVDS Differential PCB

LVDS Differential PCB thumbnail
4-layer controlled-impedance PCB template for RF/LVDS differential routing with 100 Ω differential pair design rules.

Properties

PCB material FR-4; target board thickness 0.062 in / 62 mil / 1.57 mm. Current Flux Standard 4 Layer stackup totals 1.30 mm, so confirm final fab stackup with manufacturer before impedance signoff.

Pricing & Availability

Distributor

Qty 1

Arrow

$2.85–$3.13

LCSC

$3.45

Mouser

$5.02

Verical

$3.06–$7.71

Controls