USB Sensor Node

Placement is complete: USB/power is grouped on the left/lower-left, DDS and low-level analog are central, and the output amplifier sits behind the right-edge BNC. I’m checking and tightening any remaining decoupling-placement issues now.
Created a project doc
PCB Layout Review — Programmable Function Generator
Board outline set to 100 mm × 80 mm with 2 mm rounded corners. Stackup set to 4 copper layers for USB, SPI, analog output, and multi-rail po...
View doc
PCB layout placement is complete on a 100 × 80 mm, 4-layer board: USB/power is on the left, LT3471 power is lower-left, DDS/control/conditioning are central, and the THS3091/BNC output is on the right. I ran placement, DRC, and BOM checks; details are captured in PCB Layout Review.
Open items:
  • Board is not routed yet, so airwires are expected.
  • DRC still reports exposed-pad footprint copper overlap on U3, U6, and U10.
  • Generic resistors/capacitors/inductors still need final orderable MPNs for assembly.
Suggested next steps:
  1. Repair or replace U3/U6/U10 exposed-pad footprints.
  2. Assign real MPNs/packages to generic passives and inductors.
  3. Route the PCB, then re-run full DRC.
Fix footprints and BOM
Fix footprint overlaps
Assign passive MPNs
Route the PCB
Run full checks
X1
J3
J1
U4
U9
U7 V_{SS} - C31 P1
U1 SOURCE - C2 P1
R3 P2 - U4 PA11[PA9]
R30 P2 - R31 P1
R15 P2 - R16 P1
U1 VCC - C1 P1
U4 PA7 - U5 SDATA
U6 A2 - R14 P1
U7 V_{SS} - C31 P1
U5 VDD - C7 P1
U8 VIN- - R26 P2
R32 P2 - R33 P1
U5 CAP/2.5V - C9 P1
U4 PA15 - U7 ~{CS}
U10 OUT 2 - R24 P1
U4 VBAT - U4 VREF+
R28 P2 - R29 P1
U4 PF2-NRST - R8 P2
U6 A1 - R13 P1
U5 VDD - C7 P1
U1 SOURCE - C2 P1
U1 EN - R5 P2
J1 DN1 - J1 DN2
U1 VCC - C1 P1
U1 VCC - C1 P1
U1 SOURCE - C2 P1
J1 VBUS__1 - U1 VCC
U4 VBAT - U4 VREF+
U1 EN - R5 P2
U7 V_{SS} - C31 P1
U3 VREF - C22 P1
U3 ~SHDN~/SS2 - R35 P2
U7 V_{SS} - C31 P1
U7 V_{DD} - C30 P1
U6 A1 - R13 P1
U5 VDD - C7 P1
X1 OUT - U5 MCLK
U9 VREFIO - C18 P1
U7 V_{DD} - C30 P1
U4 PA5 - U5 SCLK
U4 PF2-NRST - R8 P2
U6 A2 - R14 P1
U6 EN - R11 P2
U3 ~SHDN~/SS1 - R34 P2
U1 ILIMIT - R6 P1
U4 PA14-BOOT0 - R7 P1
U3 ~SHDN~/SS1 - R34 P2
U5 COMP - C10 P1
R20 P2 - R21 P2
U4 PA13 - J3 SWDIO/TMS
R20 P2 - R21 P2
U7 V_{DD} - C30 P1
R22 P2 - R23 P1
R28 P2 - R29 P1
U7 V_{SS} - C31 P1
U4 PA13 - J3 SWDIO/TMS
U1 SOURCE - C2 P1
U7 V_{SS} - C31 P1
U7 V_{DD} - C30 P1
J1 DP1 - J1 DP2
U4 PA5 - U5 SCLK
U7 V_{DD} - C30 P1
U6 EN - R11 P2
U5 VDD - C7 P1
U7 V_{DD} - C30 P1
R32 P2 - R33 P1
U6 A2 - R14 P1
U1 SOURCE - C2 P1
J1 DN1 - J1 DN2
U6 EN - R11 P2
U7 W - U8 VIN+
U4 PA15 - U7 ~{CS}
R4 P2 - U4 PA12[PA10]
U10 OUT 2 - R24 P1
U7 V_{SS} - C31 P1
U4 VBAT - U4 VREF+
U5 VDD - C7 P1
R3 P2 - U4 PA11[PA9]
R15 P2 - R16 P1
R32 P2 - R33 P1
U4 PA7 - U5 SDATA
U5 VDD - C7 P1
U5 VDD - C7 P1
U9 SPI2C - R10 P1
U6 D - R22 P1
U4 PA5 - U5 SCLK
U4 PA8 - R15 P1
U3 ~SHDN~/SS1 - R34 P2
U4 PF2-NRST - R8 P2
U7 V_{DD} - C30 P1
U1 SOURCE - C2 P1
U4 PA7 - U5 SDATA
R21 P1 - U10 OUT 1
U5 CAP/2.5V - C9 P1
R17 P2 - C20 P1
U1 GATE - C3 P1
R30 P2 - R31 P1
J1 DP1 - J1 DP2
U7 W - U8 VIN+
U4 VBAT - U4 VREF+
R17 P2 - C20 P1
U8 VIN- - R26 P2
U3 SW2 - L2 P2
J1 DN1 - J1 DN2
U4 PA6 - U7 SDO
U9 VREFIO - C18 P1
U3 SW2 - L2 P2
U5 VDD - C7 P1
U7 V_{SS} - C31 P1
U3 VREF - C22 P1
U5 VDD - C7 P1
U3 SW1 - L1 P2
U3 VREF - C22 P1
U7 V_{SS} - C31 P1
U4 PA5 - U5 SCLK
U8 VOUT - R26 P1
R30 P2 - R31 P1
U4 VBAT - U4 VREF+
J1 DP1 - J1 DP2
U9 VOUT - R20 P1
J1 CC2 - R2 P1
U5 COMP - C10 P1
U7 V_{SS} - C31 P1
U8 VOUT - R26 P1
U1 SOURCE - C2 P1
J1 CC2 - R2 P1
U3 SW1 - L1 P2
U4 PA7 - U5 SDATA
R4 P2 - U4 PA12[PA10]
U3 ~SHDN~/SS2 - R35 P2
U4 PA14-BOOT0 - R7 P1
R22 P2 - R23 P1
U5 VOUT - R17 P1
U6 A0 - R12 P1
R32 P2 - R33 P1
U5 VDD - C7 P1
R17 P2 - C20 P1
C25 P2 - D2 A
U9 VOUT - R20 P1
U7 V_{SS} - C31 P1
U10 -IN 2 - R24 P2
U3 SW1 - L1 P2
U10 OUT 2 - R24 P1
J1 CC1 - R1 P1
U4 PB0 - U9 ~SYNC~/A0
J1 DN1 - J1 DN2
U5 VDD - C7 P1
U6 A0 - R12 P1
U7 V_{DD} - C30 P1
J1 CC1 - R1 P1
U10 -IN 2 - R24 P2
R15 P2 - R16 P1
U4 PA4 - U5 ~FSYNC
U7 V_{DD} - C30 P1
J1 VBUS__1 - U1 VCC
U5 VDD - C7 P1
U5 VDD - C7 P1
R20 P2 - R21 P2
R28 P2 - R29 P1
J1 CC2 - R2 P1
U6 A1 - R13 P1
U7 V_{DD} - C30 P1
J1 DP1 - J1 DP2
R21 P1 - U10 OUT 1
U4 VBAT - U4 VREF+
C25 P2 - D2 A
U4 PA6 - U7 SDO
U4 PA8 - R15 P1
C25 P2 - D2 A
U7 V_{DD} - C30 P1
U6 A0 - R12 P1
U7 V_{SS} - C31 P1
U1 ILIMIT - R6 P1
U4 PF2-NRST - R8 P2
U8 VOUT - R26 P1
U1 GATE - C3 P1
U4 PA14-BOOT0 - R7 P1
U4 VBAT - U4 VREF+
U8 VIN- - R26 P2
U10 -IN 2 - R24 P2
U3 SW2 - L2 P2
U4 PA6 - U7 SDO
U5 VDD - C7 P1
U1 SOURCE - C2 P1
U9 SPI2C - R10 P1
U3 VREF - C22 P1
X1 OUT - U5 MCLK
U5 VOUT - R17 P1
U5 VDD - C7 P1
U5 VDD - C7 P1
U1 SOURCE - C2 P1
U6 D - R22 P1
U5 VDD - C7 P1
R22 P2 - R23 P1
R30 P2 - R31 P1
U4 PB0 - U9 ~SYNC~/A0
U4 PA4 - U5 ~FSYNC
U3 ~SHDN~/SS2 - R35 P2
R21 P1 - U10 OUT 1
U1 SOURCE - C2 P1
J1 CC1 - R1 P1
U5 VDD - C7 P1
R10
Resistance
10kΩ
C23
Capacitance
4.7uF
C28
Capacitance
330nF
R6
Resistance
2kΩ
C30
Capacitance
100nF
R28
Resistance
49.9Ω
C24
Capacitance
4.7uF
R35
Resistance
4.7kΩ
R34
Resistance
4.7kΩ
C25
Capacitance
1uF
R7
Resistance
10kΩ
R21
Resistance
10kΩ
C7
Capacitance
100nF
C37
Capacitance
6.8uF
R17
Resistance
100Ω
R23
Resistance
10kΩ
R4
Resistance
22Ω
C10
Capacitance
10nF
C15
Capacitance
100nF
C9
Capacitance
100nF
R9
Resistance
10kΩ
R24
Resistance
2.32kΩ
R2
Resistance
5.1kΩ
R33
Resistance
150kΩ
R1
Resistance
5.1kΩ
C6
Capacitance
10uF
C8
Capacitance
10uF
R12
Resistance
100kΩ
R13
Resistance
100kΩ
C29
Capacitance
330nF
C14
Capacitance
100nF
C2
Capacitance
10uF
R16
Resistance
10kΩ
R31
Resistance
4.99kΩ
R29
Resistance
1MΩ
C33
Capacitance
100nF
R32
Resistance
10kΩ
R3
Resistance
22Ω
R25
Resistance
1kΩ
R26
Resistance
866Ω
C4
Capacitance
1uF
C34
Capacitance
100nF
R11
Resistance
10kΩ
R5
Resistance
300kΩ
C32
Capacitance
100nF
C31
Capacitance
100nF
C1
Capacitance
1uF
C12
Capacitance
4.7uF
R27
Resistance
95.3Ω
R8
Resistance
10kΩ
R15
Resistance
45.3kΩ
R30
Resistance
69.8kΩ
C16
Capacitance
100nF
C35
Capacitance
100nF
R22
Resistance
10kΩ
R14
Resistance
100kΩ
C26
Capacitance
47pF
C18
Capacitance
150nF
C5
Capacitance
1uF
C20
Capacitance
1nF
R20
Resistance
10kΩ
C19
Capacitance
100nF
C11
Capacitance
100nF
C21
Capacitance
4.7uF
C36
Capacitance
6.8uF
C22
Capacitance
100nF
C17
Capacitance
1uF
C3
Capacitance
100pF
C13
Capacitance
100nF
C27
Capacitance
22pF
D1
J1 GND__1 - J1 GND
U7 GND - C30 P2
J1 GND__1 - J1 GND
U5 AGND - C7 P2
U2 GND - C4 P2
C20 P2 - R16 P2
U7 GND - C30 P2
U5 AGND - C7 P2
U7 GND - C30 P2
U2 GND - C4 P2
C20 P2 - R16 P2
U7 GND - C30 P2
U5 AGND - C7 P2
J1 GND__1 - J1 GND
U7 GND - C30 P2
U2 GND - C4 P2
U3 GND - C22 P2
J1 GND__1 - J1 GND
C20 P2 - R16 P2
U5 AGND - C7 P2
U3 GND - C22 P2
U2 GND - C4 P2
U2 GND - C4 P2
D2
U5 AGND - C7 P2
U3 GND - C22 P2
U3 GND - C22 P2
U2 GND - C4 P2
J1 GND__1 - J1 GND
U5 AGND - C7 P2
U5 AGND - C7 P2
U5 AGND - C7 P2
U7 GND - C30 P2
C20 P2 - R16 P2
U7 GND - C30 P2
C20 P2 - R16 P2
GND
C20 P2 - R16 P2
U2 GND - C4 P2
J1 GND__1 - J1 GND
U3 GND - C22 P2
J1 GND__1 - J1 GND
U3 GND - C22 P2
U2 GND - C4 P2
U7 GND - C30 P2
J1 GND__1 - J1 GND
GND
GND
U3 GND - C22 P2
GND
U5 AGND - C7 P2
GND
U2 GND - C4 P2
GND
GND
C20 P2 - R16 P2
GND
U5 AGND - C7 P2
GND
GND
GND
U5 AGND - C7 P2
U5 AGND - C7 P2
U7 GND - C30 P2
U2 GND - C4 P2
U7 GND - C30 P2
U5 AGND - C7 P2
C20 P2 - R16 P2
U3 GND - C22 P2
C20 P2 - R16 P2
U3 GND - C22 P2
J1 GND__1 - J1 GND
U2 GND - C4 P2
J1 GND__1 - J1 GND
U5 AGND - C7 P2
L3
Inductance
10uH
L1
Inductance
10uH
J2
U1
U2
U8
L2
Inductance
10uH
D3
U6
U10
U3
U5
U7

Refine this doc
Ask about this doc
PCB Layout Review — Programmable Function Generator
Layout Work Completed
  • Board outline set to 100 mm × 80 mm with 2 mm rounded corners.
  • Stackup set to 4 copper layers for USB, SPI, analog output, and multi-rail power routing.
  • All 90 physical components placed on the top side.
  • Functional placement zones:
    • Left edge: USB-C input J1, USB ESD and CC resistors, input protection U1.
    • Upper-left: STM32 U4, SWD header J3, USB routing passives.
    • Lower-left: LT3471 ±15 V switching supply, inductors, Schottky diodes, output capacitors, and feedback/soft-start passives.
    • Center: AD9833 DDS U5, 25 MHz oscillator X1, reconstruction/filtering and waveform mux U6.
    • Center-right: ADA4898 conditioner U10, DAC/digipot control U9/U7.
    • Right edge: THS3091 output amplifier U8 and BNC output J2.
Placement Status
  • No component body overlap or outside-board placement errors remain.
  • Routing congestion improved after spreading the central control/analog section; current layout summary reports routing space is acceptable on the 4-layer stackup.
  • All components remain top-side for simpler assembly.
DRC / Layout Checks

Table


Check AreaResultNotes
Board size / placementPassComponents fit on 100 × 80 mm board
StackupPass4-layer stackup confirmed after final board update
Component overlap / outside boardPassNo reported component placement errors in final checked set
AirwiresExpected openBoard is placed but not routed; airwires remain until routing phase
Overlapping copperOpen issue12 errors on U3, U6, and U10 exposed-pad/thermal-mount footprint geometry
Missing footprintsPassNo missing-footprint errors reported
BOM availabilityMixedMain ICs/connectors have MPNs; generic passives/inductors still need final orderable MPNs
Open DRC Issue: Exposed-Pad Footprint Copper
The overlapping-copper checks are concentrated on:
  • U3 LT3471EDD#PBF exposed GND pad area
  • U6 ADG758CPZ exposed/substrate VSS pad area
  • U10 ADA4898-2YRDZ exposed pad area
The checks appear to be caused by unnamed duplicate footprint thermal/mount pads overlapping the named exposed pad terminals. Attempting to delete the duplicate internal mount pads by UID did not succeed because those nodes are not exposed as normal editable layout nodes. This should be resolved before manufacturing by replacing/repairing those footprints or using a library footprint variant with a single correctly-netted exposed pad.
BOM Check Notes
  • 17 non-generic part groups have MPNs populated.
  • Generic passives/inductors are still generic and trigger manufacturer-part-number checks:
    • 33 resistors
    • 37 capacitors
    • 3 inductors
  • Before assembly export, select real MPNs/packages for the generic passives, especially:
    • LT3471 inductors L1/L2/L3 with adequate saturation current
    • ±15 V rail capacitors C23/C24/C25 and output amp decoupling C34-C37
    • precision feedback/gain resistors R20-R27/R30-R33
  1. Resolve U3/U6/U10 exposed-pad footprint overlap issue.
  2. Assign package and MPNs to generic passives and power inductors.
  3. Route the board, starting with power rails and high-speed/analog-sensitive nets.
  4. Re-run full DRC including airwires after routing.
  • Layout Work Completed

  • Placement Status

  • DRC / Layout Checks

  • Open DRC Issue: Exposed-Pad Footprint Copper

  • BOM Check Notes

  • Recommended Next Steps

Programmable Function Generator

Programmable Function Generator thumbnail
Programmable 1 Hz–1 MHz function generator PCB with sine, triangle, and adjustable-duty square outputs, programmable amplitude up to ±10 V using a DDS-based signal path and protected power rails.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$36.81–$51.23

Digi-Key

$20.00

HQonline

$22.03–$22.05

LCSC

$57.46–$57.88

Mouser

$67.08

TME

$10.80

Verical

$25.68–$47.67

Controls