library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Frequency_Generator is
Generic(
CLOCK_FREQ : positive := 50_000_000 -- Base clock frequency in Hz
);
Port(
clk_in : in std_logic;
clk_5hz: out std_logic;
clk_10hz: out std_logic;
clk_1khz: out std_logic;
clk_100khz: out std_logic;
clk_800khz: out std_logic
);
end Frequency_Generator;
architecture Behavioral of Frequency_Generator is
signal div_5hz, div_10hz, div_1khz, div_100khz, div_800khz : unsigned(31 downto 0);