AI Glasses Schematic Design
1:22
Clarifying component actions.
Issuing queries for design.
Planning queries and execution.
Preparing implementation plan.
Using Knowledge Base Tool.
Executing queries.
Started implementing a plan
# Goal
- Update the ESP32-C6-MINI-1 smart-glasses schematic to match the new user GPIO mapping by removing the JTAG header, adding a new push-to-talk button on GPIO23, and reassigning the I2S nets while retaining the existing Reset (EN) and Boot (IO0) buttons. Ensure the schematic passes ERC, maintains CP2102N auto-boot support, and includes proper design practices for EN pull-up and noise immunity.
# Implementation plan
1. Update the schematic components:
1. Remove the JTAG header (J2) and disconnect all related JTAG nets.
2. Retain the Reset (EN) and Boot (IO0) buttons (S1, S2).
3. Add a new momentary push-to-talk (PTT) button assigned to GPIO23 with an appropriate pull-up resistor (~10k) and a small debounce capacitor to ensure noise immunity.
2. Reassign I2S nets connections on the ESP32-C6-MINI-1 (U1):
1. Connect I2S_BCLK from ESP32-C6-MINI-1 to GPIO18.
2. Connect I2S_WS from ESP32-C6-MINI-1 to GPIO22.
3. Connect MIC_SD from ESP32-C6-MINI-1 to GPIO16.
4. Connect AMP_DIN from ESP32-C6-MINI-1 to GPIO20.
5. Update net labels accordingly.
3. Verify supporting connections and components:
1. Confirm the EN pin’s pull-up resistor and noise-reducing capacitor are correctly implemented.
2. Ensure the CP2102N (U3) DTR/RTS connections for auto-boot are correctly routed to EN/IO0 on the ESP32-C6-MINI-1.
4. Run Electrical Rules Check (ERC) and update the Bill Of Materials (BOM) to include the added PTT button.
# Success criteria
- The JTAG header (J2) is completely removed from the schematic.
- A new push-to-talk button is added on GPIO23 with proper pull-up and debounce network.
- I2S nets are reassigned correctly to GPIO18, GPIO22, GPIO16, and GPIO20.
- The schematic passes ERC and all warnings have been addressed.
- The BOM is updated to include the new push-to-talk button component.
Working on your request...
0:14
Planned updates and retrieved schematic rules
0:09
Using Knowledge Base Tool.
Started: Removing JTAG header and adding PTT parts
Inspected existing nets and ESP32 pins
0:09
Using Schematic Tool.
Started: Inspecting existing nets and pins for remap
Loaded schematic design skill guidance
0:12
Started: Removing J2 and adding PTT button network
Added 3 components and Removed 1 component
0:08
Added 1x B3FS-1002 as S3
Added 1x Generic Resistor as R10
Added 1x Generic Capacitor as C18
Remapped I2S and wired PTT network
0:56
Started: Rewiring I2S nets to new GPIOs
Updated 11 connections
0:04
Connected U1:IO18, M1:SCK, U2:BCLK to ^I2S_BCLK
Connected U1:IO22, M1:WS, U2:LRCLK to ^I2S_WS
Connected U1:IO16, M1:SD to ^MIC_SD
Connected U1:IO20, U2:DIN to ^AMP_DIN
Connected U1:IO23, R10:P1, C18:P1, S3:NO_1 to ^PTT
Connected U3:VDD, R10:P2 to ^3V3
Connected GND:GND, C18:P2, S3:COM_1 to ^GND
Disconnected U1:IO4, M1:SCK, U2:BCLK
Disconnected U1:IO5, M1:WS, U2:LRCLK
Disconnected U1:IO2 from M1:SD
Disconnected U1:IO3 from U2:DIN
Checked ERC results after schematic edits
0:13
Using Schematic Tool.
Started: Verifying EN/BOOT auto-boot and ERC cleanup
Renamed nets and connected new GPIOs
0:31
Started: Fixing I2S pin remap and CP2102N wiring issues
Using Schematic Tool...
Updated labels for 3 net labels
0:07
Renamed 958017f1-9d8f-49da-81ec-068fd6d469f3 to I2S_WS
Renamed a4d61287-a0d4-4e7e-8e56-dad936e59977 to MIC_SD
Renamed 6283f5c6-4f45-4836-ab58-41464c42a512 to AMP_DIN
Plan completed.
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Loose Cyan KITT
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Properties
Availability & Pricing
| Distributor | Qty 1 | |
|---|---|---|
| Arrow | $3.92–$7.31 | |
| Digi-Key | $14.29–$17.61 | |
| LCSC | $10.57 | |
| Mouser | $20.64 | |
| TME | $7.18 | |
| Verical | $8.11–$28.99 | |
Assets
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