Schematic-to-Layout Gate Closure
Verdict
PCB LAYOUT GATE: PASS
Fresh validation at 2026-08-24T01:26:53Z returned 0 ERROR, 0 WARNING, 0 OPEN, 0 UNCERTAIN for the requested ERC/passive checks and 0 unresolved missing-footprint, missing-MPN, and parts-availability checks.
1. Production passive policy
All 117 generic passives (70 capacitors and 47 resistors; no generic inductors are present) now have production packages, electrical ratings, manufacturer, and MPN properties while preserving values and connectivity.
- Resistors: 0603 thick-film, 1%, 0.1 W. Yageo RC0603FR-07 series MPNs were assigned by value. This covers USB-C CC, USB3320 RBIAS, BQ24074 programming, regulator feedback, reset/power-good, storage pull-ups, controls, and audio isolation. The 0.1 W rating matches the TPS63802 reference design for the 511 kΩ/91 kΩ/100 kΩ network and greatly exceeds actual dissipation in the bias and pull networks.
- General 100 nF decouplers: 0603 X7R, ±10%, 50 V Fenghua 0603B104K500NT. The high voltage rating gives strong DC-bias margin at 1.8–5 V rails without forcing 0402 density.
- 1 µF / 2.2 µF: Murata 0603 X5R/X7R, 10 V. C15/C16 satisfy the STM32H743 2.2 µF, ±20%, ESR <100 mΩ VCAP requirement. C45 is 2.2 µF X7R for USB3320 VDD33 stability (<1 Ω ESR requirement). C69 is 2.2 µF ceramic for TPS79318 stability.
- Regulator bulk: C39/C40/C43 use the TPS63802 datasheet-listed Murata GRM188R61A226ME15, 22 µF, 10 V, 0603. C41/C42/C44 were increased to 0805 and assigned Murata GRM21BZ71A226KE15L, 22 µF, 10 V, X7R, matching the TPS62A02 reference design and providing effective-capacitance margin. BQ24074 C36–C38 remain 4.7 µF/10 V/0603 ceramic, within its 1–10 µF IN and 4.7–47 µF BAT/OUT requirements.
- Clock exceptions: C27/C28 (16 pF) and C29/C30 (18 pF) were changed to 0402 C0G/NP0-family, 5% parts to minimize oscillator-loop parasitics. Final values remain explicitly bench-tunable for measured PCB stray capacitance.
- Audio exceptions: C55/C56 were corrected from unrealistic 220 µF/1210 ceramics to Nichicon UWT1A221MCL1GS, 220 µF, 10 V, polarized aluminum electrolytic, 6.3 × 7.7 mm SMD. P1 is verified on the codec-output side, so the positive terminal faces the codec common-mode voltage. C57/C58 remain 10 µF/10 V/0805 X5R for line-output coupling.
- Low-leakage/timing: C54 and C70 use 50 V C0G parts for reset filtering and TPS79318 reference bypass.
2. Battery connector and NTC assembly
Board connector: J6 remains JST S3B-PH-SM4-TB(LF)(SN), a keyed 3-position, 2.0 mm side-entry SMT PH header rated 2 A with AWG24 wire and 100 V. The sourced mating assembly is:
- Housing: JST PHR-3
- Contacts: 3 × JST SPH-002T-P0.5S, AWG30–24
- Board pin order by JST circuit number: 1 = BAT+, 2 = pack NTC, 3 = GND
The schematic connectivity was verified as J6-1→VBAT, J6-2→BAT_NTC_PACK/JP1, and J6-3→GND. Connector family, housing/contact details, polarity, pin order, and current rating are documented on J6. Source:
JST PH series drawing.
Thermistor interface: Production packs must use a
10 kΩ at 25°C NTC with Semitec 103AT-2 curve, Beta 3435 K. The BQ24074 datasheet specifically calls for 103AT-2 and sets nominal charge suspension around 0°C/50°C using its 75 µA TS bias. R43 remains a development-only fixed 10 kΩ fallback selected by JP1; it is not the production thermal sensor. Sources:
BQ24074 datasheet and
Semitec AT thermistor data.
External procurement constraint: the exact protected 1-cell LiPo pack vendor/capacity/dimensions remain an enclosure/procurement choice. Any approved pack must be protected, use the documented PHR-3 harness order, accept ≥0.8 A charge, and support ≥1.5 A continuous discharge (system peak budget is about 1.24 A at depleted battery). This is now a controlled procurement assumption rather than an unresolved PCB mating fact.
3. Display FPC orientation and connector correction
The DLC0240PZG Rev. 1.4 mechanical drawing establishes:
- 40 contacts, 0.5 mm pitch, 19.5 mm first-to-last contact span
- 0.30 ± 0.05 mm stiffened insertion thickness
- The conductive/exposed contact side is opposite the stiffener
- Detail A marks pin 1 at the end labeled “1” and pin 40 at the opposite end
- The free flex end inserts straight into the receptacle with its conductive side facing the connector contacts
The former J3, Würth 68714014022, was a
top-contact connector and was therefore removed. J3 is now
JUSHUO AFC01-S40FCA-00 (LCSC C262674), a 40-position, 0.5 mm, horizontal
bottom-contact hinged/ZIF connector for 0.3 mm FPC. All panel nets were transferred pin-for-pin; pins 1, 35, and 38 remain explicit panel NCs, and mounting terminals 41/42 are explicit NCs. Connector evidence:
LCSC/JUSHUO AFC01-S40FCA-00.
Exact mutation scope
- Replaced: J3
68714014022 → AFC01-S40FCA-00; preserved the complete 40-pin display mapping and explicit NCs.
- Battery metadata updated: J6 and R43.
- All resistors updated: R1–R28 and R31–R49 (47 populated resistor designators).
- All generic capacitors updated: C1–C64 and C68–C73 (70 populated capacitor designators).
- Package changes: C27–C30 0603→0402; C41/C42/C44 0603→0805; C55/C56 1210 non-polarized→6.3 × 7.7 mm polarized SMD electrolytic.
- Connectivity changes: only the controlled J3 connector replacement; all validated architecture and functional nets were preserved.
Fresh checks
- Electrical Rule Checks + passive checks: 0 errors, 0 warnings, 0 open, 0 uncertain.
- Missing footprint / manufacturer part number / parts availability review: 0 unresolved findings.
- Headphone capacitor polarity verification: C55/C56 P1 connect to
HP_L_CODEC/HP_R_CODEC; P2 connect to the jack-side coupled nets.
PCB LAYOUT GATE: PASS
No genuine schematic-to-layout blocker remains in the assigned scope. Layout has not been started.