Unified the ^+3V3 rail so all STM32 supply pins on U4 (VBAT/VDDA/VDDx) and the opto pullup on U2 and enable on U1 are on a single +3V3 net.
Isolated U4PA0_WKUP onto PULSER_OPTO_OUT (no longer tied into the prior fragmented power net).
Removed the leftover single-pin net-portal artifacts (IC1 EN - R5 P2, LDO_EN, EFUSE_ILIM, EFUSE_EN, and related portal duplicates).
Success criteria review
❌ ERC/DRC not yet verified clean. When removing portal artifacts, Flux warned that connections on those removed portal symbols were destroyed, so connectivity must be re-verified/repaired before ERC can be considered clean.
✅ +3V3 rail is now unified and U4 supply pins are tied to +3V3.
✅ U4 PA0 is on PULSER_OPTO_OUT, and U2 output is no longer shorted to +3V3.
✅ J1 is present as a 1x8 2.54 mm right-angle header with placeholder MPN (TBD-1x8-RA-2.54mm).
❌ Gerber/BOM/Pick-and-Place exports not generated (must be after clean ERC/DRC).
Next steps
I need to run a targeted netlist verification and re-connect any pins that were only connected through the deleted portal symbols (then re-run ERC/DRC and export). That requires additional tool execution, but I am currently blocked from continuing in this session.