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Project Specification

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Project Specification Project Overview
  • Status: Review
  • Device: Two-board thermal imaging platform using an ESP32-S3 main board and an MLX90640BAA 32x24 thermal sensor satellite.
  • Purpose: Acquire, process, interpolate, and transmit thermal frames over Ethernet, Wi-Fi, BLE, or native USB.
Intended Use
  • Debug-friendly first prototype for indoor integration in an enclosure.
  • Sensor is separated from MCU, Ethernet, and power heat sources to reduce thermal measurement bias.
  • Main-to-satellite cable length is at most 20 cm.
What the Device Should Do
  • Read MLX90640 thermal frames over 3.3 V I2C.
  • Process frames on an ESP32-S3.
  • Provide 10/100 Ethernet through a W5500 and RJ45 MagJack.
  • Accept isolated IEEE 802.3af PoE power and USB-C power.

Power Budget

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Power Budget Scope
Pre-schematic budget for the ESP32-S3 thermal camera main board and MLX90640 satellite. Values are conservative engineering estimates pending confirmation against the exact selected part revisions and datasheets.
3.3 V Loads Regulator Design Target
  • Add approximately 25 percent peak-current engineering margin: 735 mA x 1.25 = approximately 919 mA.
  • Select a 3.3 V regulator rated at least 1 A; 1.2-1.5 A is preferred for transient and thermal margin.
  • Estimated 3.3 V output power:
    • Typical: 3.3 V x 0.406 A = 1.34 W.
    • Peak: 3.3 V x 0.735 A = 2.43 W.
LDO Thermal Check
For a 5 V to 3.3 V LDO:
  • Typical dissipation: (5.0 V - 3.3 V) x 0.406 A = 0.69 W.
  • Peak instantaneous dissipation: (5.0 V - 3.3 V) x 0.735 A = 1.25 W.

flux

The Project Specification and Power Budget are created. The review selects a 1.2-1.5 A-class 3.3 V buck instead of a small LDO and flags legacy 500 mA USB operation as a peak-load constraint; I’m now building both schematic sections.
Thought for 5 mins 44 sec
Thought for 35 sec
Thought for 11 sec
Awaiting 1 background task
Received notification from "Two Board Schematic" that it finished — picking the work back up.

flux

The executor populated 30 components covering the ESP32-S3, W5500, AG9905-MTB PoE module, USB-C, AP63203 buck regulator, power OR-ing, RJ45, and MLX90640 satellite hardware. I also created the Project Specification and Power Budget files.
Open items
  • The project currently reports 0 nets, so the components are not yet electrically wired.
  • Both board sections still need connectivity checks, ERC review, and correction.
  • The power budget must be reconciled against the exact selected parts.
Execution is paused because no ACUs are currently available. Once ACUs are available, the next action is to wire both sections, verify every power/interface pin, and clear ERC findings before starting PCB layout.
Wire both sections
Check missing essentials
Verify power budget
Check ERC issues
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Project Specification
Project Overview
  • Status: Review
  • Device: Two-board thermal imaging platform using an ESP32-S3 main board and an MLX90640BAA 32x24 thermal sensor satellite.
  • Purpose: Acquire, process, interpolate, and transmit thermal frames over Ethernet, Wi-Fi, BLE, or native USB.
Intended Use
  • Debug-friendly first prototype for indoor integration in an enclosure.
  • Sensor is separated from MCU, Ethernet, and power heat sources to reduce thermal measurement bias.
  • Main-to-satellite cable length is at most 20 cm.
What the Device Should Do
  • Read MLX90640 thermal frames over 3.3 V I2C.
  • Process frames on an ESP32-S3.
  • Provide 10/100 Ethernet through a W5500 and RJ45 MagJack.
  • Accept isolated IEEE 802.3af PoE power and USB-C power.
  • Support native USB programming, CDC, and JTAG.
  • Provide Wi-Fi 2.4 GHz and BLE 5 through the ESP32-S3 module.
Main Features
  • ESP32-S3-WROOM-1 module.
  • W5500 hardware TCP/IP Ethernet controller on SPI.
  • Isolated PoE module in the Ag9905M class, nominal 5 V output.
  • USB-C USB 2.0 device and 5 V input.
  • Protected power OR-ing into 5V_SYS.
  • Efficient 3.3 V conversion sized for ESP32 radio current transients.
  • RESET, BOOT, status LED, and accessible rail/signal test points.
  • Separate MLX90640BAA satellite PCB with local decoupling.
System Architecture
Diagram



  
    
  
  
    
  














SPI

10BASE-T and node_100BASE-TX

I2C over cable

USB D+ and D-









"RJ45 PoE Input"
"Isolated PoE Module\n5V_PoE"
"USB-C Device Port\n5V_USB and USB 2.0"
"Reverse Current Protected OR-ing"
"5V_SYS"
"3.3V Buck Regulator"
"ESP32-S3-WROOM-1"
"W5500 Ethernet Controller"
"MLX90640 Satellite PCB"
Hardware Subsystems
Main board
  • Compute: ESP32-S3-WROOM-1 with EN reset network, GPIO0 BOOT control, and status LED.
  • Ethernet: W5500, 25 MHz crystal network, SPI control, interrupt, reset, and PoE-compatible MagJack.
  • PoE: Isolated 37-57 V input module with center-tap connection and isolation-boundary discipline.
  • USB-C: Sink/device configuration with independent 5.1 kOhm CC resistors, VBUS protection, and low-capacitance ESD protection for D+/D-.
  • Power path: Reverse-current-safe OR-ing of 5V_PoE and 5V_USB. Use an efficient buck regulator rather than a small LDO because the worst-case 3.3 V load can dissipate more than 1 W in a linear regulator.
  • Debug: RESET and BOOT buttons plus test points for 5V_SYS, 3V3, GND, SPI, I2C, W5500 reset/interrupt, and ESP32 EN/GPIO0 where practical.
Satellite board
  • MLX90640BAA in TO-39 package.
  • JST-SH 1.0 mm 4-pin polarized connector: GND, 3V3, SDA, SCL.
  • 100 nF local VDD decoupling plus optional small bulk capacitance.
  • ESD protection appropriate for an internal cable.
  • No duplicate I2C pull-ups; pull-ups reside on the main board.
Interfaces and Connections

Table

InterfaceAssignment
W5500 MOSIESP32 GPIO11
W5500 SCKESP32 GPIO12
W5500 MISOESP32 GPIO13
W5500 CSESP32 GPIO10
W5500 INTESP32 GPIO9
W5500 RSTESP32 GPIO14
MLX90640 SDAESP32 GPIO4
MLX90640 SCLESP32 GPIO5
USB D-ESP32 GPIO19
USB D+ESP32 GPIO20
BOOTESP32 GPIO0
Status LEDESP32 GPIO2
Power and Runtime Expectations
  • Primary source: IEEE 802.3af PoE through an isolated 5 V module, approximately 1.8 A capability.
  • Alternate source: USB-C at 5 V.
  • USB-C must not be assumed to provide more than the current advertised by the source. Full simultaneous radio and Ethernet peak operation may exceed a legacy 500 mA USB budget.
  • No battery or runtime requirement.
Power Tree and Power Budget
See the separate Power Budget project file. Design targets:
  • 3V3 regulator continuous rating at least 1 A, preferably 1.2-1.5 A with good transient response.
  • Power OR-ing path and PoE path sized above the calculated 5 V peak with margin.
  • USB operation remains source-current dependent unless CC current advertisement is detected or firmware limits peak operation.
Manufacturing and Assembly Expectations
  • Four-layer, 1.6 mm FR4, 1 oz copper.
  • L1 signals/components, L2 uninterrupted GND, L3 segmented power, L4 secondary signals/GND fill.
  • First revision favors 0603/0805 passives, clear functional grouping, and accessible test points.
  • Main board target is approximately 70 x 50 mm, adjustable after confirmed footprints.
Firmware-Relevant Hardware Requirements
  • Native ESP32-S3 USB Serial/JTAG programming.
  • Manual BOOT and RESET controls.
  • W5500 SPI and interrupt support.
  • I2C operation initially up to 400 kHz; validate cable capacitance before Fast Mode Plus.
  • Firmware should support Ethernet, Wi-Fi/BLE, thermal-frame acquisition, and source-aware power management if USB current detection is added.
Physical Design Expectations
  • RJ45 and USB-C adjacent on the same board edge and protruding 0.5-1 mm beyond the PCB outline.
  • ESP32 antenna at a board edge with no copper on any layer beneath the antenna and at least 5 mm surrounding clearance, subject to the exact module datasheet.
  • Four corner mounting holes, final M2.5 or M3 choice deferred.
  • Main PCB should remain compact but is not aggressively miniaturized.
  • Enclosure internal height target approximately 16-18 mm.
Important Design Decisions
  • Two-PCB architecture selected to reduce MLX90640 thermal bias.
  • Direct 3.3 V I2C selected for the at-most-20 cm internal cable.
  • Debuggability and assembly access prioritized over minimum area.
  • Buck regulation selected provisionally instead of an AP2112K/AMS1117-class LDO because the calculated dissipation can exceed safe small-package thermal limits.
  • Main-board I2C pull-ups selected as one pair for the whole bus; satellite contains no second pair.
Assumptions
  • The PoE module and MagJack are available with verified library symbols/footprints or can be replaced by documented equivalents.
  • The satellite sensor uses the MLX90640BAA wide-angle variant.
  • USB-C is a sink/device port without USB Power Delivery.
  • I2C cable is internal, short, and routed away from noisy PoE/switching nodes.
  • Exact mounting-hole diameter remains open until enclosure hardware is chosen.
Change Notes
  • Initial specification created from the supplied French technical requirements.
  • Architecture split into main and satellite PCBs.
  • Cable length fixed at at most 20 cm.
  • First revision designated as debug-friendly and approximately 70 x 50 mm.

  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • System Architecture

  • Hardware Subsystems

  • Main board

  • Satellite board

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Manufacturing and Assembly Expectations

  • Firmware-Relevant Hardware Requirements

  • Physical Design Expectations

  • Important Design Decisions

  • Assumptions

  • Change Notes