Power Architecture Review
V5 buck output is directly tied to U1:5V, and the RP2040 Zero’s 5 V/VUSB/VSYS node is directly connected internally, so the fix should split V5 into buck-side and RP2040-side rails with a Schottky/ideal-diode power path; I also flagged Q1 source/drain orientation and C11’s likely net/role mismatch.VIN_28V_RAW, VIN_28V_PROTECTED, V5, V3V3_MOTOR, GND, SW, BOOT, and FB.VIN_28V_RAW, VIN_28V_PROTECTED, V5, V3V3_MOTOR, SW, BOOT, and FB set to 0.4 mm; GND set to 0.25 mm.VIN_28V_RAW, VIN_28V_PROTECTED, V5, V3V3_MOTOR, GND, SW, BOOT, and FB.MOTOR_A, MOTOR_B, and motor-driver control outputs as needed.TRIG_IN, TRIG_SENSE, MOTOR_FWD, MOTOR_REV, and related GPIO/resistor/indicator connections.Routing phase status — 2026-05-05
Power Routing Phase
Verification
Remaining routing sequence
Notes
ryanf