Power Architecture Review

ryanf

ryanf

take a look at all these components I want to make sure that the RP240 doesn't back power the buck converter and that the power switches to buck converter power when I power through this connector. is the current architecture correct? make a design doc outlining this problem.

flux

0:11

Thought for 5 sec

Thought for a moment

I’ll audit the existing power architecture around the RP2040 Zero, buck converter, and connector power path, then write a project file documenting whether back-powering is prevented and what changes are needed.

flux

4:49

Thought for 2 sec

Created 4 tasks.

1/4 Inspect schematic nets and components around RP2040 Zero, buck converter, connector power input, and power-switching devices

Thought for 2 sec

Completed design checks — found 36 issues.

Read schematic.

Thought for 4 sec

2/4 Check relevant datasheet details for buck converter and RP2040 Zero power behavior

Thought for 5 sec

Read U2 datasheet for LMR14030 EN pin behavior input voltage s.

Read U1 datasheet for RP2040-ZERO module 5V pin 3V3 pin USB po.

Read Q1 datasheet for QM6015D P channel MOSFET pinout body dio.

Read schematic.

Read "[Datasheet for QM6015D] QM6015D P channel MOSFET pinout body diode direction maximum VGS recommended reverse polarity protection orientation" in QM6015D.pdf.

Read QM6015D.pdf.

Thought for 5 sec

Read U3 datasheet for MP6513 VCC supply operating voltage inpu.

Found 10 results for RP2040-Zero WaveShare schematic 5V pin USB diode back power external 5V.

Read schematic.

Thought for 3 sec

Read waveshare.com.

Thought for 16 sec

3/4 Determine whether the existing architecture prevents back-powering and auto-selects buck power correctly

Read 11 knowledge entries.

Thought for 13 sec

Thought for 5 sec

4/4 Create/update a project file documenting the issue, findings, and recommended architecture

Thought for 45 sec

Thought for 3 sec

4/4 tasks completed.

Thought for a moment

I reviewed the power architecture and created Power Backfeed Architecture Review.
Verdict: the current architecture is not correct for preventing RP2040 Zero USB/5 V back-power into the buck output network. The V5 buck output is directly tied to U1:5V, and the RP2040 Zero’s 5 V/VUSB/VSYS node is directly connected internally, so the fix should split V5 into buck-side and RP2040-side rails with a Schottky/ideal-diode power path; I also flagged Q1 source/drain orientation and C11’s likely net/role mismatch.
Recommend ideal diode
Check Q1 orientation
Run ERC/DRC
Propose rail names
Add wiring table

Finished working

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Design Notes
Routing phase status — 2026-05-05
Power Routing Phase
  • Inspected power-related nets: VIN_28V_RAW, VIN_28V_PROTECTED, V5, V3V3_MOTOR, GND, SW, BOOT, and FB.
  • Re-optimized placement for routing access: power input and trigger terminals are on the left edge, motor terminal is on the right edge, power components are grouped near the lower-left/lower-middle section, and motor driver is near the motor output terminal.
  • Configured stackup intent on the existing 4-layer board: layer 2 as Ground Plane and layer 3 as Power Plane.
  • Applied power-net trace-width rules: VIN_28V_RAW, VIN_28V_PROTECTED, V5, V3V3_MOTOR, SW, BOOT, and FB set to 0.4 mm; GND set to 0.25 mm.
  • Regenerated neckdown geometry successfully: 1 polygon created, 0 failures.
Verification
  • Board remains 70 mm × 45 mm, 4-layer, with all 22 components placed inside the outline.
  • Current DRC status: missing footprints, invalid layers, overlapping copper, and floating copper checks pass.
  • Remaining blocker: airwires still present, currently 27 reported by DRC. This indicates physical copper traces have not yet been completed for all schematic nets.
Remaining routing sequence
  1. Complete physical routing for power nets: VIN_28V_RAW, VIN_28V_PROTECTED, V5, V3V3_MOTOR, GND, SW, BOOT, and FB.
  2. Route motor nets: MOTOR_A, MOTOR_B, and motor-driver control outputs as needed.
  3. Route control/trigger signals: TRIG_IN, TRIG_SENSE, MOTOR_FWD, MOTOR_REV, and related GPIO/resistor/indicator connections.
  4. Run final DRC cleanup and verification until airwires and critical manufacturing checks are clear.
Notes
The available automated actions completed placement optimization, stackup setup, net rule assignment, neckdown generation, and DRC verification. Final physical trace routing still requires a full routing pass before production export.

    Routing phase status — 2026-05-05

    Power Routing Phase

    Verification

    Remaining routing sequence

    Notes

Documents

    Design Notes

    Buck Converter Manufacturing Readiness

    Power Backfeed Architecture Review

Assets

Assets are files uploaded to this project which can be used in various ways.

RP2040 Zero 28V Motor Controller thumbnail
Compact RP2040 Zero motor controller with protected 28 V input, 3.3 V reversible motor H-bridge output, USB programming, active-high trigger input, and 3.5 mm screw terminals.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$2.59–$3.38

Digi-Key

$2.34–$2.80

HQonline

$0.90

LCSC

$1.27

Mouser

$7.94

TME

$8.49

Verical

$3.68–$5.05

Controls