Breadboard Schematic for Electromagnetic Visualizer


The exported PDF is wrong because it shows PCB layers/footprints/copper instead of a readable schematic.
Please convert this project into a clean documentation schematic only.
Requirements:
  • Do NOT create PCB layout.
  • Do NOT show PCB footprints.
  • Do NOT show copper layers.
  • Do NOT show pads only.
  • Use schematic symbols, not footprint symbols.
  • Draw visible schematic wires.
  • Keep this as a breadboard prototype documentation schematic.
Create a clean one-page schematic with these blocks from left to right:
  1. Power rails
  2. BC547 LC oscillator
  3. LM339 comparator
  4. ESP32 + OLED + calibration button
Use visible wires and net labels.
Main signal path:
+5V → L1 → OUT_OSC
OUT_OSC → BC547 collector
OUT_OSC → C1 47nF → EMIT
EMIT → C2 47nF → GND
EMIT → RE 1k → GND
BASE biased by R1 47k to +5V and R2 20k to GND
OUT_OSC → C3 10nF → SIG_IN
SIG_IN → LM339 pin 5
VREF → LM339 pin 4
LM339 pin 2 → COMP_OUT
R6 4.7k from +3V3 to COMP_OUT
COMP_OUT → R7 1k → ESP32 GPIO27
OLED VCC → +3V3
OLED GND → GND
OLED SDA → ESP32 GPIO21
OLED SCL → ESP32 GPIO22
SW1 from ESP32 GPIO14 to GND
Power:
ESP32 5V → +5V
ESP32 3V3 → +3V3
ESP32 GND → GND
LM339 pin 3 → +5V
LM339 pin 12 → GND
All grounds common.
Important:
  • LM339 output pull-up R6 must connect to +3V3, not +5V.
  • ESP32 GPIO is not 5V tolerant.
  • ESP32 must not connect directly to OUT_OSC.
  • U1:VP is intentionally unused and should remain No Connect.
After revising, make the schematic fit on one readable page for screenshot or print-to-PDF.
I’ll revise the project into a clean one-page documentation schematic only: schematic symbols, visible wiring/net labels, left-to-right functional blocks, and no PCB layout work.
Created a clean one-page breadboard documentation schematic with schematic symbols, visible wires, and net labels — no PCB layers, copper, footprints, or pads-only view.
Files:
  • commentFileId-2ae3401e777c4b5ef68a6cc9afa4b62758362e5df30bab23c7ceb1b8a0313b6e.svg

    Clean schematic SVG
  • Printable schematic HTML — open this and use browser Print → Save as PDF.
I also added Breadboard Assembly Schematic to the project files documenting that this schematic-only output is the correct assembly reference. The live netlist was rechecked; the only remaining ERC issue is the intentional U1:VP No Connect, as requested.
Export PDF version
Check schematic accuracy
Create assembly guide
Generate BOM list
Add firmware starter

Q1
U3 OUTPUT1 - R6 P2
U2 SCL - U1 IO22
U3 OUTPUT1 - R6 P2
RE
Resistance
1 kΩ
C3 P2 - R5 P1
L1 P2 - Q1 C
L1 P2 - Q1 C
R4
Resistance
20 kΩ
R3 P2 - R4 P1
C2
Capacitance
47 nF
C3
Capacitance
10 nF
Q1 E - RE P1
NOTE2
U3 OUTPUT1 - R6 P2
L1 P2 - Q1 C
U1 5V - L1 P1
U2 SCL - U1 IO22
U1 3V3 - R3 P1
R3 P2 - R4 P1
Q1 E - RE P1
Q1 E - RE P1
U1 5V - L1 P1
Q1 B - R1 P2
R7
Resistance
1 kΩ
C5
Capacitance
100 uF
NOTE1
U1 5V - L1 P1
Q1 B - R1 P2
U1 3V3 - R3 P1
U2 SDA - U1 IO21
R3 P2 - R4 P1
C4
Capacitance
100 nF
R3
Resistance
20 kΩ
L1 P2 - Q1 C
U1 5V - L1 P1
C3 P2 - R5 P1
R3 P2 - R4 P1
SW1 P1 - U1 IO14
U1 5V - L1 P1
Q1 B - R1 P2
R1
Resistance
47 kΩ
R7 P2 - U1 IO27
U1 5V - L1 P1
U1 3V3 - R3 P1
U1 3V3 - R3 P1
R7 P2 - U1 IO27
U2 SDA - U1 IO21
R6
Resistance
4.7 kΩ
SW1 P1 - U1 IO14
R5
Resistance
47 kΩ
Q1 E - RE P1
C3 P2 - R5 P1
R2
Resistance
20 kΩ
C1
Capacitance
47 nF
GND
GND
U3
U1 GND_3 - R2 P2
U1 GND_3 - R2 P2
U1 GND_3 - R2 P2
U1 GND_3 - R2 P2
U1 GND_3 - R2 P2
U1 GND_3 - R2 P2
U1 GND_3 - R2 P2
U1 GND_3 - R2 P2
U1 GND_3 - R2 P2
U1 GND_3 - R2 P2
L1
Inductance
Handmade / tune empirically H
U1
SW1
U2

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