I completed the previously missing USB-C connections and advanced the Pico-derived schematic to 64 components and 46 nets. This includes separate CC pull-downs, protected USB data, the fused power path, BOOTSEL/reset test points, and additional decoupling; your working GPIO assignments and BLK-to-3.3 V connection are preserved.
The schematic is saved, but it is not yet ready for PCB placement or ordering. My review found these remaining items:
Display footprint: the existing eight-pad placeholder is not a verified solder interface. Header dimensions, receiving-hole sizes and pin-1 registration need manufacturer confirmation or physical measurements.
13 ERC errors remain: connectivity inspection suggests pin-type/power-source recognition issues rather than missing wires, but these still need proper resolution—not suppression.
USB power compliance: startup, pre-enumeration and suspend current remain unverified with the permanently enabled display.
Component verification: select concrete regulator bulk capacitors, clarify the flash exposed-pad requirement, and finish NFC footprint binding checks.
The saved schematic-completion-record documents the changes and blockers, and prototype-bring-up-plan records testing guidance. Next session should close those issues before placement; routing, the NFC antenna and enclosure-fit validation remain deferred.
Dockit Till Display: USB-connected counter device displaying a QR URL and offering the same URL through NFC. Status: prototype schematic development; layout requires review checkpoint.
Intended Use
Shop till PC USB connection, customer phone QR scan or NFC tap. Several assembled PCB trials before production to validate operation and housing fit. This is electronics-first work; the mechanical package remains PROVISIONAL.
What the Device Should Do
Run the existing working Pico application unchanged where hardware permits.
Enumerate as USB CDC and accept the URL from the till PC.
Show a QR code and provide the same URL through the NFC tag.
Keep display backlight on, as in the working prototype.
Main Features
Fixed RP2040, ST25DV64KC-IE6S3, ER-TFTM1.54-1 module; Pico-reference flash/crystal and power; USB-C, status LED, BOOTSEL/RESET, SWD programming access; directly soldered display module.
Mechanical System Architecture
PROVISIONAL approximately 54 ×54 mm rounded-square PCB, four M2 corner mounting positions. Target case ≤60 ×60 mm and strictly <15 mm thick. Display centered on top with minimal verified gap and no top-side SMD underneath. All SMD on bottom. USB-C on one edge. Enclosure CAD and exact height/clearance validation are deferred until PCB placement.
Diagram
Electrical System Architecture
Use the Pico development board as the reference circuit, not as a soldered-on module: integrate its RP2040 core, reference flash/crystal and Pico-style power circuit into the new PCB. The latest user instruction supersedes the AP2112 LDO selection in the original brief. Resolve the exact official Pico regulator/passives and sourcing within construction. Retain USB-C rather than the Pico's micro-USB connector, with the required Type-C device termination and protection.
Diagram
Hardware Subsystems
Compute/storage/clock: RP2040, W25Q16JV family 2 MB flash, ABM8-272-T3 12 MHz crystal and official support circuitry.
Power: official Pico reference topology and used components; no battery or externally accessible supply requested. Prefer reference circuit continuity over previous LDO plan. Preserve Pico sensing/control connections where applicable.
USB: USB-C USB 2.0 device, separate CC pull-downs, ESD, 27 Ω D+/D− series resistors, shield/ground and protected VBUS.
UI: fixed module on an 8-contact plated-through-hole solder footprint; status LED on GP25. No bare-panel FPC connector.
NFC: fixed SO-8 chip, I2C pull-ups and decoupling, optional GPO/GP6, antenna AC0/AC1 and two parallel DNP C0G tuning capacitor sites. GP7 remains unused because this package has no LPD pin; see Feasibility Review for sourced evidence.
Debug: BOOTSEL pulls QSPI_SS low through reference resistor, RESET pulls RUN low; bottom SWD programming pads as requested in original brief.
Interfaces and Connections
Latest working pin attachment takes precedence for implemented behavior.
Table
Display contact
Connection
GND
GND
VCC
3V3
SCL
GP18 / SPI0 SCK
SDA
GP19 / SPI0 TX
RES
GP21
DC
GP20
CS
GP17
BLK
3V3, always on
SPI0 mode 3, 10 MHz as supplied by user. NFC SDA GP4, SCL GP5, power 3V3, common GND. GP25 status LED. Optional GP6 GPO with pull-up. Do not add GP22 switching to the prototype's confirmed default-on BLK connection; reserve GP22 for future control. No GP7 power-down connection.
The attachment says it records I2C speed and X-NUCLEO jumper settings, but those values are not actually present in its contents; do not invent them. Existing feasibility evidence derives default 7-bit NFC addresses 0x53/0x57.
Power and Runtime Expectations
USB host-powered, no battery, continuous use while powered. USB current and suspend behavior must be validated against actual firmware; copying Pico hardware does not certify complete-device USB power compliance.
Power Tree and Power Budget
USB VBUS → protection/reference power path → Pico-reference regulator →3V3→ MCU/flash, display/BLK, NFC, LED; internal MCU core regulator as official reference. Original brief's <150 mA total estimate remains PROVISIONAL, not a measured limit. Detailed current budget, regulator margins, startup and suspend measurements remain prototype validation items.
Manufacturing and Assembly Expectations
Two-layer target, 1.6 mm nominal PCB (thinner only after physical validation); bottom-side JLCPCB SMD assembly and hand-soldered display module. Fixed three primary devices cannot be substituted. Reference flash/crystal remain preferred for unchanged firmware. Exact catalog codes and assembly stock must be verified; spreadsheet is flexible. Preserve a 500 mA-class PTC protection intent, subject to source/derating checks. Display through-hole size, pad geometry, orientation and physical module registration must be sourced before footprint creation; no guessed fabrication-critical dimensions.
Firmware-Relevant Hardware Requirements
Preserve supplied GPIO mapping, Pico-compatible flash boot/clock and reset/boot functions. Optional new inputs must not interfere with existing firmware. Backlight remains directly enabled. Prototype firmware binary/source not supplied, so unchanged operation and USB descriptors/power management cannot yet be certified.
Physical Design Expectations
Do not place/routethe complete PCB in this stage. Create and verify the display mating footprint as part of schematic component preparation, then review schematic before placement. RF perimeter, USB metal/transition, mounting heads, and display metal require joint floorplanning; the prior all-layer zero-other-traces antenna rule needs a deliberate localized USB feedthrough exception. NFC resonance/read range require trials with the assembled display and case.
Important Design Decisions
Latest instruction chooses Pico-reference power components instead of AP2112.
Treat 'use Pico development board and its used components' as reproducing its circuit on the custom board, consistent with the brief's fixed bare RP2040 and low height target, not mounting an entire Pico.
Fixed display is the module with soldered pin row; no ZIF/FPC.
GP7/LPD request is physically impossible for selected SO-8 chip; omit it without changing chip.
Prototype iterations precede production; do not claim manufacturing readiness yet.
Assumptions
Plastic/nonconductive enclosure, indoor counter use, approximate PCB envelope and thickness provisional. No exact case CAD, firmware files, tap-distance target or measured assembly heights supplied. Display geometry and pin-one orientation must be confirmed from manufacturer source before mating footprint is finalized.
Change Notes
2026-10-10: Started schematic from user's confirmed prototype wiring and Pico power-reference direction. Records preserve the original constraints unless explicitly superseded here.