USB-C QR Display PCB Design

Thought for 4 mins 50 sec
Thought for 7 sec
2/3 Independently review the schematic and resolve blocking findings.

Complete the Pico-derived schematic and verify display solder-interface facts.

Independently review the schematic and resolve blocking findings.

Save verification results and pause for schematic-to-layout approval.

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Reading "schematic-completion-record" project doc.
"Schematic Review Blockers" completed.

flux

I completed the previously missing USB-C connections and advanced the Pico-derived schematic to 64 components and 46 nets. This includes separate CC pull-downs, protected USB data, the fused power path, BOOTSEL/reset test points, and additional decoupling; your working GPIO assignments and BLK-to-3.3 V connection are preserved.
The schematic is saved, but it is not yet ready for PCB placement or ordering. My review found these remaining items:
  • Display footprint: the existing eight-pad placeholder is not a verified solder interface. Header dimensions, receiving-hole sizes and pin-1 registration need manufacturer confirmation or physical measurements.
  • 13 ERC errors remain: connectivity inspection suggests pin-type/power-source recognition issues rather than missing wires, but these still need proper resolution—not suppression.
  • USB power compliance: startup, pre-enumeration and suspend current remain unverified with the permanently enabled display.
  • Component verification: select concrete regulator bulk capacitors, clarify the flash exposed-pad requirement, and finish NFC footprint binding checks.
The saved schematic-completion-record documents the changes and blockers, and prototype-bring-up-plan records testing guidance. Next session should close those issues before placement; routing, the NFC antenna and enclosure-fit validation remain deferred.
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Schematic

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Schematic completion record
Batch status: independent safe schematic edits completed; overall design NOT complete or fabrication-ready. Latest schematic mutation: 7282a000. Final ERC inspected 2026-10-10 09:11 UTC.
Completed
  • USB-C VBUS, paired D+/D−, separate 5.1kΩ CC pull-downs, ESD data and VBUS connections. All four shield terminals now explicitly grounded; three floating-pin errors resolved.
  • Power path USB_VBUS → F1 1206L050/15YR → VBUS_FUSED → D2 → VSYS → RT6150B-33GQW → 3V3. Raw VBUS retained for ESD rail and GPIO24 sensing.
  • L1 replaced with sourced XAL4020-222MEB 2.2µH; verified high-current ratings, not claimed to be exact original Pico MPN. C15/C16 retain official Pico 47µF nominal values with 16V/1206 procurement requirements; supplier DC-bias validation remains open.
  • NFC U3 updated to helper-verified SO8N published version 071555ae-5da0-4390-9c50-b37571507513. Existing I2C/GPO/AC wiring preserved. GP7 and V_EH unused; GP22 unused. Two 0402 DNP tuning sites remain unvalidated RF provisions.
  • TP7 BOOTSEL through R2 1kΩ to QSPI CS; TP8 RUN reset. C23/C24 local 100nF flash/display decoupling added. Resistor requirements 0.1W/1%; capacitor voltage requirements recorded. Corrected Q1 datasheet link.
  • Read-only full schematic and net inspection confirmed display GP17/18/19/20/21, BLK to 3V3, NFC GP4/5/6, regulator support wiring, QSPI, ADC3 sense, and 1V1 from VREG_VOUT. Empty VSYS_SENSE_RETURN deleted.
Failed / blocked
  • Clean ERC: 13 Errors remain: two U1 DVDD missing-power, one U2 VIN missing-power; ten DS1/U3 undriven signal/power/ground inputs. Net inspection confirms intended connections, suggesting library pin-type/power propagation issues, but these are not proven artifacts and were NOT suppressed. Library metadata remediation and fresh ERC required.
  • Display mating footprint: DS1 has no usable footprint in parent scene-tree inspection. Manufacturer header cross-section/tolerances or receiving-board finished-hole specification, unambiguous pin-1/row registration and seating plane required. Nominal module outline and visible pitch do not establish solder fit; mounting-hole dimensions are not header drills. No guessed geometry authored.
  • Exact preferred W25Q16JVSSIQ unavailable in library; retained Pico UX package. Exposed-pad NC follows official Pico drawing, but vendor UX pad instruction still needs clarification.
  • Certified worst-case power budget: firmware operating modes unspecified. 200mA at 3V3 is only a provisional design envelope, NOT a demonstrated worst-case maximum. F1 hold is temperature dependent (0.5A at20°C, 0.35A at60°C); actual load, inrush and thermal test required.
  • TP7/TP8 size property accepted as nonstandard; physical probe-pad dimensions not confirmed. Adjacent ground access needed during placement.
Unattempted / deferred
  • Schematic visual rearrangement remains default columns; no supported arrangement mutation established in this batch.
  • PCB outline, placement, routing, NFC coil, USB return/feedthrough, bottom-side arrangement and enclosure stack validation deferred. Mixed ERC/DRC/rating query reports 172 matching violations; first100 were airwires, expected for unrouted design. Do not interpret this as a complete DRC pass.
  • Authentic-model SPICE, RF simulation, production exports and manufacturing release not performed. No simulation proof claimed.
Source trail
  • Official Pico Rev3 schematic was downloaded and visually inspected: input/output bulk both47µF, L1 2.2µH, flash CS pull-up NOFIT. Readable render:

    commentFileId-159118127e84aea8c934381f1b0b1087f1a1689661a40ef82a562cfb51f86701

    https://cdn2.flux.ai/flux-comment-files/files/commentFileId-159118127e84aea8c934381f1b0b1087f1a1689661a40ef82a562cfb51f86701.png?GoogleAccessId=fleet-worker%40graviton-mvp.iam.gserviceaccount.com&Expires=4945222695&Signature=Pf6w%2BGcbBx80OKlFju2rAY6Uzua%2FHTXm9q7aRlsO4k4bnukg6u0nX8CMD1JHDqj3%2BSJJeBkvpu1OzcrqAyl9mcCLPNs9a6Pv9FaCA0UULR6HyllzlnwtpWBo9NC9l1UrkT4DotdI0rOk7gi1wDJY%2BtlZtSbJpSBHGuUz0W3Y1jrPvnzDuFJdAU54Ht1bSyQwxUs0huDRxKJYCVSn5wjhii38uvcKJV8FjNmKd1xDFCxY3VsPAj%2FSrkea03AySQOO1U6r7JAdC7vJ6titGTcuBo55S5H5pSrdQ4ZFnz6Rv6u7i7uDhuY3Yxaav33AbN2D3kZq%2BqmHXUspXlGyPxkDmQ%3D%3D
  • Regulator: https://www.components-store.is/datasheets/3b/RT6150B-33GQW.pdf
  • Q1: https://www.diodes.com/assets/Datasheets/DMG1012T.pdf
  • Flash: https://stm32-base.org/assets/pdf/devices/W25Q16JV.pdf
  • Helper NFC package-verification and display mating-footprint-status documents contain detailed package/mechanical evidence in their respective part projects.

  • Completed

  • Failed / blocked

  • Unattempted / deferred

  • Source trail