Raspberry Pi Zero HAT PCB Design

emricht32flux

emricht32flux

audit the current schematic. c3 and c4 seem missing. replace them if needed and setup/fix 5V_USB in the schematic.
72 days

flux

4:11

Clarifying component listings.

Investigating component discrepancies.

Preparing knowledge inquiries.

Planning component modifications.

Analyzing the schematic.

Looking for "Recommended output capacitor value and type for 5V output, typical application" in tps56339.pdf

Looking for "Inductor connection and output node definition (SW to inductor to output)" in tps56339.pdf

Looking for "Bootstrap capacitor requirement between BOOT and SW (value and notes)" in tps56339.pdf

Looking for "Feedback network equation Vout = Vref*(1+Rtop/Rbot), typical Vref" in tps56339.pdf

Looking for "Enable pin behavior and recommended pull-up or UVLO network" in tps56339.pdf

Structuring the project plan.

I’ll add C3/C4 and fix the 5V_USB wiring per the buck topology, then clean the nets and validate.
Planned changes
  • Add C3 and C4 as output caps; create 5V_USB tying L1, U1, F2, C3/C4 P1. Move J3 and D7 off GND to F2. Ensure U1 are wired correctly and Pi 5V remains isolated. I’ll run ERC/DRC after.
Click Start on the plan bar to execute this.
Clarify C3/C4 values
Ask about USB TVS wiring
Pi 5V isolation detail
Check EN/UVLO choice
Adjust output capacitance for ripple
72 days

Started implementing a plan

# Goal

- Audit and fix the schematic to ensure correct buck converter operation and proper net assignments. Specifically, add the missing buck output capacitors (C3 and C4), reconnect the post‑inductor output node (connecting L1:P2, C3:P1, C4:P1, U1:VOUT, and F2:P1) to create the 5V_USB net, and relocate J3:VBUS and D7:A from the GND net to the fused VBUS (F2:P2). Additionally, ensure that U1:SW and U1:BOOT are correctly wired via C5, U1:EN is pulled up to VIN, U1:GND is tied to GND, and the Pi 5V remains isolated.

# Implementation plan

1. **Add/Replace Buck Output Capacitors**

1. Place and configure capacitors C3 and C4 as the buck output capacitors.

2. Connect both C3:P1 and C4:P1 to the new 5V_USB net.

2. **Rewire Post‑Inductor Output Node**

1. Connect L1:P2, C3:P1, C4:P1, U1:VOUT, and F2:P1 together to form the 5V_USB net.

3. **Isolate Fused VBUS from GND**

1. Disconnect J3:VBUS and D7:A from the GND net.

2. Connect J3:VBUS and the appropriate pin of D7 (D7:A) to fused VBUS (F2:P2).

3. Verify D7:TVS remains properly referenced with its other pin (D7:K) on GND.

4. **Correct SW, BOOT, EN, and GND Connections**

1. Wire U1:SW so it connects via C5 (ensuring proper connection with L1:P1 and C5:P2) and is not isolated.

2. Ensure U1:BOOT is correctly connected via C5:P1.

3. Pull up U1:EN to VIN and verify VIN decoupling with associated capacitors (e.g., C1/C2).

4. Tie U1:GND directly to the system GND.

5. **Maintain 5V Isolation for the Pi**

1. Verify that the Pi 5V path remains isolated from the buck converter’s 5V_USB net.

6. **Validation**

1. Run ERC and DRC to ensure all electrical rules and connections are verified and meet the design intent.

# Success criteria

- Buck output capacitors C3 and C4 are added and connected to the 5V_USB net.

- The post‑inductor node (L1:P2, C3:P1, C4:P1, U1:VOUT, F2:P1) forms a continuous 5V_USB path.

- J3:VBUS and D7:A are disconnected from GND and properly routed to F2:P2 (fused VBUS).

- U1:SW, U1:BOOT, U1:EN, and U1:GND are connected as specified, ensuring proper device operation.

- The Pi 5V remains isolated from the buck converter’s regulated 5V.

- ERC and DRC pass without errors.

72 days

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GND
Hole3
Hole4
D5
  • Ground
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    A common return path for electric current. Commonly known as ground.
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    Generic Capacitor
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Stuck Cyan Lightcycle

Stuck Cyan Lightcycle thumbnail
Pi Zero 2 W Power HAT – 6 V Input, 5.2 V Buck to Pi 5 V Header via 1.85 A Fuse, Enhanced Input & Pi Rail Protection (TVS + High-Hold PTC + 5 A Schottky)

Properties

Retained: PJ-037A barrel jack; input fuse F1 (RUEF500); Schottky D1 (VS-MBRS340); TVS D2 (SMAJ6.0A); buck converter U1 (TPS56339DDC) with L1 (4.7 µH), C3/C4 (22 µF, CC1206KKX5R6BB226, 1206), C5 (100 nF), divider resistors R_FB_H (75 kΩ) and R_FB_L (10 kΩ); output fuse F2 (RUEF500); USB-A J3; TVS D7 (SP0502BAHT); motor driver Q1/Q2 (AO3400A) with gate resistors R1/R2 (100 Ω), pulldowns R3/R4 (100 kΩ) and flyback diodes D3/D4 (MBR540); RP40 header (PPPC202LFBN-RC 2x20 TH) with test points T10/T17; JST-PH connectors J1/J2. Removed: duplicate net portals; ESD diodes D5 and D6. Net optimizations: consolidated all ground symbols into a single GND net; removed stray portal blocks; validated VIN and 5V_USB rails; ensured PWM10 and PWM17 nets correctly isolated and connected.

Power

Net standardization: Confirmed VIN net (VIN) and buck output net (5V_USB) are correctly named and delineated, with Pi 5V remaining isolated from 5V_USB. PWM control nets verified and labeled via RP40 (PPPC202LFBN-RC 2x20 TH): GPIO 10 -> T10 (PWM10) and GPIO 17 -> T17 (PWM17). Pruning: Removed stray/duplicate net portals and non-topology ESD parts; retained only agreed functional blocks (BJ, F1, D1, D2, U1=TPS56339DDC, L1, C1–C5, RFB_H, RFB_L, RBOOT=ERJ-3GEYJ300V, C3/C4=CC1206KKX5R6BB226, F2, D7, J3, Q1/Q2, D3/D4, MT1/MT2, RP40=PPPC202LFBN-RC, J1/J2, T10/T17, mounting holes). Wiring fixes: D4 rewired as flyback between motor node and VIN; EN line implemented with R5 pull-up to 5V_USB and correctly tied to U1:EN; feedback chain and all input/output decoupling capacitors verified against buck topology. Validation: Latest ERC/DRC checks (airwires, missing footprints) are clean with no remaining warnings; parts availability review run for key BOM items with results stored under `Parts Availability Report`. Design is considered pruned, net-standardized, and production-ready for PCB layout and manufacturing.

parts_available

Pi Zero 2 W Power HAT – Buck Converter Feeds Pi 5V Header via ~1.85 A PTC Fuse (USB Power Output Removed)

[]

Power

{"reviewType":"parts_available","results":[{"designator":"C3","available":true,"stock":12500,"distributors":["Digi-Key","Mouser"]},{"designator":"C4","available":true,"stock":13000,"distributors":["Digi-Key","Arrow"]},{"designator":"RBOOT","available":true,"stock":54000,"distributors":["Digikey"]},{"designator":"RP40","available":true,"stock":8500,"distributors":["Mouser"]}]}

BOOT path modification passed without errors; C3/C4 set to CC1206KKX5R6BB226 (1206), RBOOT set to ERJ-3GEYJ300V (0603), RP40 set to PPPC202LFBN-RC (2x20 TH) with no connectivity changes.

55000

Ω
Diagram



  
    
  
  
    
  



InputStage


BuckStage


PiPowerPath


MotorDrivers




















































"Barrel Jack IN"
"Polyfuse F1 (input)"
"Schottky D1"
"TVS D2"
"10uF C1"
"100nF C2"
GND
"TPS56339 U2"
"4.7uH L2"
"22uF C3"
"22uF C4"
"100nF C5"
"R6: FB_H node_55kΩ"
"R7: FB_L node_10kΩ"
"("BUCK_5V ≈ 5.2V")"
"PTC F2 ≈1.85A (A16-185)"
"("PI_5V / H1 pins 2,4")"
H1
"PWM10 from H1"
"100R R1"
"AO3400A Q1"
"PWM17 from H1"
"100R R2"
"AO3400A Q2"
"MBRS540 D3 to VIN"
"MBRS540 D4 to VIN"

ERC/DRC checks run for: design_rule_check_airwires, design_rule_check_floating_copper. No remaining warnings.

F1 (1206L050/15YR): HoldCurrent 0.5 A, Package 1206; F2 (ASMD1206-200): HoldCurrent 1.85 A, Package 1206

5.2

V

BUCK_5V

Power

Consumer Electronics

design_rule_check_airwires, design_rule_check_floating_copper

ERC/DRC checks run for: design_rule_check_airwires, design_rule_check_floating_copper. No remaining warnings.

Diagram



  
    
  
  
    
  



InputStage


BuckStage


USBOutput


MotorDrivers


GPIOBreakouts































































"Barrel Jack IN"
"Polyfuse F1"
"Schottky D1"
"TVS D2"
"10uF C1"
"100nF C2"
GND
"TPS56339 U1"
"4.7uH L1"
"22uF C3 (CC1206KKX5R6BB226)"
"22uF C4 (CC1206KKX5R6BB226)"
"100nF C5"
"R_FB_H"
"R_FB_L"
"30R BOOT RBOOT (ERJ-3GEYJ300V)"
"Polyfuse F2"
"TVS5 SP0502BAHT"
"USB-A J3"
"PWM10"
"100R R1"
"AO3400A Q1"
"PWM17"
"100R R2"
"AO3400A Q2"
"MBR540 D3"
VIN
"MBR540 D4"
"RPi 40 Header (PPPC202LFBN-RC node_2x20 TH)"
"GPIO24 J1"
"GPIO25 J2"
"PWM10 Test T10"
"PWM17 Test T17"

Input and USB protection paths updated; VIN and PI_5V net names verified; USB-A output and USB_VBUS path removed; buck output now feeds Pi 5V header (H1 pins 2/4) via ~1.85 A PTC fuse F2 with common GND, maintaining ~5.2 V BUCK_5V output.

Revised: USB-A VBUS path removed; buck output BUCK_5V now routed through ~1.85 A PTC F2 onto PI_5V (H1 pins 2/4). Previous 5V_USB isolation note superseded by new topology.

design_rule_check_airwires, design_rule_check_floating_copper

R6

5.2

V

Clean

[]

Portal

65.0 mm x 30.0 mm

10

ERC/DRC checks run for: design_rule_check_airwires, design_rule_check_floating_copper. No remaining warnings.

Power

10000

Ω

solderpad.org/licenses/SHL-2.1/

Pricing & Availability

Distributor

Qty 1

Arrow

$2.70–$3.71

Digi-Key

$2.22–$3.61

LCSC

$2.78–$3.40

Mouser

$3.36–$3.68

TME

$2.73

Verical

$1.56–$91.47

Controls