PoE Ultrasonic Sensor Node Design

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Below is a detailed recommendation for the layer stackup and trace parameters to target a 100 Ω differential impedance for your Ethernet pairs:
Recommended 2-Layer PCB Stackup
  • Top Layer:
    • Purpose: Signal layer for high-speed differential pairs and other routing.
    • Copper Weight: Typically 1 oz (≈35 µm).
    • Trace Environment: Use microstrip routing; traces on the top layer will reference the bottom continuous ground plane.
  • Bottom Layer:
    • Purpose: Solid ground plane for return paths and impedance control.
    • Coverage: Ideally, a full-plane ground to provide a reliable reference for the top-layer signals.
  • PCB Overall Thickness:
    • A standard value of 1.6 mm is common.
    • The effective dielectric height between the top copper layer and the bottom ground plane should ideally be kept low (commonly in the range of 5–6 mil or around 0.127–0.15 mm) to help maintain controlled impedance on the top layer.
  • Dielectric Constant (Er):
    • Use typical FR4 values (Er ≈ 4.3–4.7). Verify with your PCB fabrication house as this factor influences impedance calculations.
Differential Pair Trace Parameters
Based on the above stackup, simulation and empirical guidance (using typical microstrip equations or PCB impedance calculators) suggest:
  • Differential Trace Width: Approximately 10 mil (0.254 mm)
  • Spacing (Gap) Between Traces: Approximately 7 mil (0.178 mm)
  • Target Differential Impedance: Approximately 100 Ω
Note: These values are common starting points for 1 oz copper on a 1.6 mm board when you have a ground plane 5–6 mil below the top copper. In practice, you should use an impedance calculator or simulation tool (e.g., Saturn PCB Toolkit) to fine-tune the dimensions based on your specific stackup details (e.g., actual dielectric thickness, FR4 material variations, and fabrication tolerances).

Summary Table

ParameterRecommendation
Board Type2-layer PCB
Board Thickness1.6 mm
Copper Weight (Top Layer)1 oz (≈ 35 µm)
Top LayerSignal layer (microstrip configuration)
Bottom LayerContinuous Ground Plane
Dielectric Height (Top-to-Ground)~5–6 mil (≈0.127–0.15 mm)
FR4 Dielectric Constant (Er)Approximately 4.3–4.7
Differential Trace Width~10 mil (0.254 mm)
Differential Spacing~7 mil (0.178 mm)
Target Differential Impedance100 Ω
By ensuring that your stackup maintains a low and consistent dielectric separation between the top layer and the ground plane, and by using the recommended trace dimensions, you’ll be well on your way to achieving 100 Ω differential impedance. Always confirm these dimensions with an impedance calculator (considering your specific PCB manufacturer’s process) for final verification.
Would you like to receive any additional recommendations regarding layer stackup details or further PCB design tips before you begin routing?
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