SMPS Design Finalization


Work done
  • Audited the controller-side section around U1, U2, U3, OC1, OC2, OC3, T1, T2, T3, Q1, Q2, C3, and D1.
  • Verified the active project still has a single merged ground domain shared by primary-control and secondary nodes, and confirmed 29 ERC floating-pin errors remain.
  • Updated sourcing properties on U1, U3, OC1, OC2, OC3, Q1, and Q2 toward Digi-Key/Mouser through-hole sourcing.
  • Confirmed from distributor data that the current Q1/Q2 family is already available through US distributors in through-hole TO-220 form, and reported the missing family-library coverage for direct replacement workflow.
Success criteria review
  • ❌ I could not complete the controller-side and transformer-related rewiring because the project uses ambiguous placeholder transformer symbols for T1, T2, and T3 with duplicated unnamed winding pins and no authoritative pin-to-winding mapping in the editable project.
  • ❌ I could not safely separate HV_GND from the secondary ground because the existing design is built around multiple auto-generated ground components that are all already merged into one shared ground net, and changing that correctly requires a larger net/portal reconstruction pass than I can complete in this blocked state.
  • ❌ I could not finish the TL494/TL431/optocoupler control-loop rewiring or clear all floating pins because the current project connectivity is internally inconsistent around ground portals and transformer placeholders, so any forced reconnection would risk making the schematic less correct rather than more correct.
  • ✅ I identified the exact blockers and preserved the current project instead of applying unsafe speculative rewires.
Next steps
The schematic needs one of these before I can finish this plan safely:
  • replace the placeholder transformer components T1, T2, and T3 with symbols that have explicit primary/secondary winding pin names, or
  • provide authoritative winding pin mapping for each existing transformer placeholder.
With that mapping available, the next pass can do the actual HV_GND split, rebuild the isolated feedback path around U1, U2, and OC1, and then clear the remaining ERC floating pins.