CM5 Ethernet Switch

Thought for 10 sec

I’ll verify both packages against Microchip’s authoritative land-pattern data, correct the exposed pads without changing signal-pad mappings, and rerun DRC to prove the 68 internal copper errors are resolved.

Thought for 15 mins 44 sec

flux

Manufacturer comparison is still in progress; the footprint geometry is being checked dimension-by-dimension before any pad override is accepted. I’ll continue through the DRC verification.

Thought for 20 mins 23 sec

Awaiting 1 background task

Thought for 9 sec

Checking U2 U3 Footprint Repair progress…

Thought for 9 sec

Awaiting 1 background task

"PCB Footprint Repair" completed.

Thought for 8 sec

flux

The footprint repair has completed. I’ll reconcile its manufacturer dimensions and edits against the board, then independently rerun overlapping-copper DRC and confirm U2/U3 placement and connectivity were preserved.

Worked for 1 min 32 sec

flux

U3 was corrected against Microchip’s land pattern, clearing 64 of 68 copper errors while preserving placement and connectivity. U2 remains unchanged with four errors because its exact recommended PCB land dimensions could not be authoritatively retrieved; details are in U2/U3 Footprint Repair Report.

Open item: obtain Microchip package specification 00000049BZ for the LAN7431 YXX package, then correct U2 without guessing.

Files

Pins

Symbol

Layout

3D View

PCB Placement Report

Scope Status

Table

Item	Status	Result
Core CM5 → LAN7431 → KSZ9477 placement	Completed	U1, U2, and U3 placed as a compact left-to-right signal chain with U2 PCIe-facing orientation and U3 RGMII-facing orientation.
Six MagJack support groups	Completed	J1–J6 were not moved; their CT capacitors and LED resistors were grouped immediately behind their owning connectors with central escape space preserved.
Ethernet decoupling and bulk placement	Completed	C30–C80 moved to bottom-side perimeter rings around U2/U3; bulk and bias/reset/strap support placed locally.
25 MHz clock placement	Completed	Y1/C86/C87 and Y2/C88/C89 placed adjacent to their IC clock pins.
Input/power grouping	Completed	Existing protection and regulator stages were consolidated into compact upper-board groups; J7 remained unchanged and accessible.
Routing	Unattempted (out of scope)	No traces or vias were added, removed, or rerouted.
Footprint-internal copper cleanup	Failed / blocked	68 pre-existing overlapping-copper errors remain inside the U2/U3 exposed-pad footprint constructions; placement cannot correct internal footprint geometry.

Final Key Coordinates

Coordinates are board-centered millimetres; rotations are counter-clockwise.

Table

Ref	Function	X (mm)	Y (mm)	Rotation
U1	Compute Module 5	-60.00	14.00	270°
U2	LAN7431 PCIe Ethernet controller	-11.50	-18.00	90°
U3	KSZ9477 managed switch	9.00	-14.00	180°
Y1	LAN7431 25 MHz crystal	-2.58	-21.72	0°
Y2	KSZ9477 25 MHz crystal	21.00	-8.50	0°
J1	LAN port 1 MagJack	-57.50	-48.43	0°
J2	LAN port 2 MagJack	-34.50	-48.43	0°
J3	LAN port 3 MagJack	-11.50	-48.43	0°
J4	LAN port 4 MagJack	11.50	-48.43	0°
J5	LAN port 5 MagJack	34.50	-48.43	0°
J6	WAN MagJack	57.50	-48.43	0°
J7	DC barrel input	-75.00	45.00	0°
J8	12 V terminal input	15.00	41.95	0°
U4	Input protection/eFuse	27.00	32.00	0°
U5	5 V regulator	47.00	33.00	0°
U6	Regulator stage	72.00	33.00	0°
U7	Regulator stage	-15.00	48.00	0°
U8	Regulator stage	25.00	50.00	0°

Placement Distance Summary

Table

Relationship	Approximate result	Target / interpretation
Y1 centre to nearest U2 XI/XO pin	5.2 mm	Meets the ≤6 mm crystal target.
Y1 to C86 / C87 centres	2.8 mm / 3.0 mm	Load capacitors are immediately adjacent to the crystal.
Y2 centre to nearest U3 XI/XO pin	3.6 mm	Meets the ≤6 mm crystal target.
Y2 to C88 / C89 centres	3.5 mm / 3.2 mm	Load capacitors are immediately adjacent to the crystal.
U1 body edge to U2 body edge	15.6 mm	Compact PCIe chain with a clear routing corridor.
U2 body edge to U3 body edge	6.7 mm	Short RGMII channel with usable escape width.
U2 0603 bypass centre to package edge	approximately 0.9–2.3 mm	Consistent with close per-pin bypass placement.
U3 0603 bypass centre to package edge	approximately 1.4–2.4 mm	Consistent with close per-pin bypass placement; bottom placement preserves top escape.
MagJack support parts behind connector body	approximately 4.5–8.5 mm	Local CT/LED grouping while leaving the pair escape corridor open.

Functional Grouping

J1: C90–C93, R17, R30
J2: C94–C97, R18, R19
J3: C98–C101, R31, R32
J4: C102–C105, R33, R34
J5: C106–C109, R35, R36
J6: C110–C113, R37, R38
U2 bypass ring: C38–C41, C63–C70, C74–C80 on Bottom
U3 bypass ring: C30, C31, C33–C62, C71–C73 on Bottom
U2 clock: Y1, C86, C87
U3 clock: Y2, C88, C89

Verification Evidence

Final placement-specific DRC review found no component-body overlap, component-outside-board, keepout, edge-placement, or pad-access-clearance violations.
Final crystal-loop and decoupling-placement review returned no error or warning results.
Connectivity inspection confirmed the preserved logical chains:
- PCIe nets between U1 and U2, including TX, reference clock, reset, clock request, wake, and receive-side source nets.
- RGMII TX/RX buses and clocks between U2 and U3.
- LAN1–LAN5 MDI nets from U3 to J1–J5.
- WAN MDI nets from U1 to J6.
- LAN7431_XI/XO through Y1/C86/C87 and KSZ9477_XI/XO through Y2/C88/C89.
No schematic connections, net names, footprints, stackup, board outline, or layout rules were changed.

Remaining Pre-existing Errors

The DRC still reports 68 overlapping-copper errors, exactly the same count observed before placement work. The UIDs identify internal footprint elements rather than inter-component placement collisions:

U2 LAN7431: exposed pad EP overlapping internal thermal-via/mount elements.
U3 KSZ9477: exposed/ground pad element c852966a...ed2e9677 overlapping numerous internal footprint mount elements.

These errors require correcting or replacing the U2/U3 footprint constructions; moving components cannot resolve them. The board is also intentionally unrouted, so the existing airwire report remains outside this placement-only task.

Scope Status
Final Key Coordinates
Placement Distance Summary
Functional Grouping
Verification Evidence
Remaining Pre-existing Errors