CM5 Ethernet Switch

flux

I could not retrieve or reconcile the executor’s completed report, and no further project changes were verified in this session.
The last confirmed requested scope remains:
  • 180 × 120 mm board outline
  • Six-layer stackup
  • Preserved connector edge assignments
  • Restored/organized CM5 → LAN7431 → KSZ9477 → RJ45 schematic flow
  • U2/U3 placement inside the enlarged board
  • Post-change ERC, DRC, and connectivity verification
Execution stopped because your ACUs ran out.
D

dgobc

continue

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The resumed implementation is still running; the executor is applying the board/stackup and coordinated schematic/PCB placement changes. I’ll continue through verification rather than stop mid-change.
Received notification from "Schematic PCB Layout" that it finished — picking the work back up.

flux

The Schematic PCB Layout executor reached completed status, but I could not retrieve and reconcile its final report before tool access ended. Therefore, I cannot safely confirm which board resize, six-layer stackup, schematic arrangement, U2/U3 placement, or verification changes actually landed.
Remaining work:
  • Retrieve the executor’s final report.
  • Inspect the board outline and stackup.
  • Confirm connector edge assignments and U1/U2/U3 placement.
  • Verify schematic connectivity, ERC, component bounds, overlaps, and DRC.
  • Fix any incomplete or failed items from that review.
Execution stopped because your ACUs ran out.
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Pins

Symbol

Layout

Preview

CM5 Pin-Type Audit
Scope
Audit of the current 200-pin Raspberry Pi Compute Module 5 symbol (fc230c89-e73c-416e-afab-e9d67cd4a23b) against the official CM5 datasheet pinout. The symbol contains all 200 connector pins. This audit focuses on electrical terminal types and highlights related protocol metadata errors that can affect ERC or controlled-impedance handling.

Table

PinsSignalsRecommended electrical type
1–2, 7–8, 13–14, 22–23, 32–33, 42–43, 52–53, 59–60, 65–66, 71, 74, 98, 107–108, 113–114, 119–120, 125–126, 131–132, 137–138, 144, 150, 155–156, 161–162, 167–168, 173–174, 179–180, 185–186, 191–192, 197–198GNDGround / power input
3–6, 9–12Ethernet MDI pairsPassive differential
15, 17Ethernet active-low LED drivesOutput
16FAN_TACHOInput
18ETHERNET_SYNC_OUTBidirectional preferred; output is acceptable for default use
19FAN_PWMOpen-collector/open-drain output
20EEPROM_nWPInput
21LED_nACTOutput
24–31, 34–41, 44–51, 54–56, 58GPIO and ID_SC/ID_SDBidirectional
57SD_CLKOutput
61, 63–64, 67–70, 72SD_DAT0–7Bidirectional
62SD_CMDBidirectional
73SD_VDD_OVERRIDEInput
75SD_PWR_ONOutput
76VBATInput (optional 2.5–3.5 V RTC supply; not a mandatory main-power input)
77, 79, 81, 83, 85, 875 V inputsPower input
78GPIO_VREFPower input
80, 82SCL0, SDA0Bidirectional/open-drain bus
84, 86CM5_3.3V outputsPower output
88, 90CM5_1.8V outputsPower output
89, 91–94, 96, 99, 101–102Disable, button, boot, CC, PMIC and OTG/CLKREQ controlsInput
95LED_nPWROutput
97, 100CAM_GPIO0, CAM_GPIO1Bidirectional GPIO
103, 105USB 2.0 D−/D+Passive differential or bidirectional
104PCIe_nWAKEInput
106PCIe_PWR_ENOutput
109PCIe_nRSTOutput
110, 112PCIe reference clock outputsPassive differential (output direction may be documented separately)
111VBUS_ENOutput
115–124MIPI0 and PCIe RX/TX pairsPassive differential; direction metadata should distinguish PCIe RX from TX
127–142MIPI0 plus USB3 port 0Passive differential; USB3 RX/TX and USB2 D+/D− must use USB metadata
143, 149, 151, 153HDMI hotplug and CECInput
145, 147, 199, 200HDMI SDA/SCLBidirectional
146, 148, 152, 154, 158, 160, 164, 166, 170, 172, 176, 178, 182, 184, 188, 190HDMI TMDS outputsPassive differential (output direction may be documented separately)
157, 159, 163, 165, 169, 171USB3 port 1Passive differential; USB3 RX/TX and USB2 D+/D− must use USB metadata
175, 177, 181, 183, 187, 189, 193–196MIPI1 lanesPassive differential
Confirmed incorrect terminal types

Table

PinSignalCurrent symbol typeCorrect typeImpact
20EEPROM_nWPBidirectionalInputCan hide output-driver conflicts; this is a strap/write-protect input.
21LED_nACTBidirectionalOutputIncorrectly permits an external driver on an LED output.
57SD_CLKBidirectionalOutputSD host clock is driven by CM5.
62SD_CMDInputBidirectionalSD command line changes direction during responses.
80SCL0InputBidirectional/open-drainI2C clock can be held low by a target for clock stretching and can be repurposed as GPIO.
84CM5_3.3V output APower inputPower outputReverses power-source semantics and can produce incorrect ERC results.
86CM5_3.3V output BPower inputPower outputSame issue as pin 84.
88CM5_1.8V output APower inputPower outputReverses power-source semantics.
90CM5_1.8V output BPower inputPower outputReverses power-source semantics.
100CAM_GPIO1 (currently named CAM_GPIO0)OutputBidirectionalIt is GPIO35 and may be used as GPIO/bus signal; the pin name is also wrong.
104PCIe_nWAKENot connectedInputPrevents legitimate PCIe wake wiring and incorrectly implies the physical pin is unavailable.
106PCIe_PWR_ENNot connectedOutputPrevents legitimate PCIe power-control wiring.
111VBUS_ENInputOutputCauses the current false Missing Power ERC error and reverses driver direction.
Conditionally incorrect or lower-severity type issues

Table

Pin(s)SignalCurrent typeRecommended handling
18ETHERNET_SYNC_OUTOutputPrefer bidirectional because the datasheet says it may be configured as an input; output is acceptable if the symbol represents only the default function.
19FAN_PWMOutputPrefer open-collector/open-drain output to represent the required external pull-up/driver behavior.
76VBATInput in the current backing symbolKeep as Input. The placed U1 still uses an older part version that treats it as Power In, causing the false ERC error.
94, 96CC1, CC2InputInput is reasonable for the CM5 power-sink implementation; passive/analog would also avoid over-constraining the CC network.
PCIe, HDMI, MIPI, Ethernet and USB high-speed lanesDifferential signalsPassivePassive is acceptable for connector/module symbols. Direction should be carried in pin descriptions/roles rather than changed if driver-conflict ERC would become noisy.
Protocol metadata errors independent of terminal type
The USB 3.0 pins inherited from CM4 camera/display positions still carry obsolete MIPI metadata in the current symbol:
  • Pins 128/130 are USB3 port 0 RX but are classified as MIPI CSI, group MIPI_CSI0, pair MIPI_CSI0_D0.
  • Pins 134/136 are USB2 D+/D− for USB3 port 0 but are classified as a MIPI data lane.
  • Pins 140/142 are USB3 port 0 TX but are classified as a MIPI clock pair.
  • Pins 157/159, 163/165, and 169/171 have the equivalent stale MIPI DSI metadata for USB3 port 1.
These should be changed to USB 3.0/USB 2.0 metadata with the appropriate targets:
  • USB3 SuperSpeed RX/TX: 85 Ω differential, unique RX/TX pair identities per port.
  • USB2 D+/D−: 90 Ω differential, unique USB2 pair identity per port.
The current stale metadata requests 100 Ω MIPI routing, which is electrically incorrect and could cause the PCB router to apply the wrong impedance and length-matching constraints.
Naming and metadata corrections
  • Pins 84/86 and 88/90 should be named CM5_3.3V(OUTPUT) and CM5_1.8V(OUTPUT), not CM4_*.
  • Pin 100 should be CAM_GPIO1, not CAM_GPIO0.
  • Pin 124’s datasheet description contains an apparent text typo saying “TX positive”; the signal name PCIe_TX_N is authoritative.
  • Ensure the symbol’s USB port numbering and pair roles remain unique so port 0 and port 1 do not pair with each other.
Priority repair list
  1. Correct pins 84, 86, 88 and 90 to Power Output.
  2. Correct pin 111 to Output and retain pin 76 as Input.
  3. Correct pins 104 and 106 from Not Connected to Input and Output.
  4. Correct the stale USB3/USB2 impedance and pair metadata on pins 128–142 and 157–171.
  5. Correct SD_CLK, SD_CMD, SCL0, EEPROM_nWP and LED_nACT terminal types.
  6. Correct pin 100 name/type and model FAN_PWM as open-drain.

  • Scope

  • Recommended pin-type table

  • Confirmed incorrect terminal types

  • Conditionally incorrect or lower-severity type issues

  • Protocol metadata errors independent of terminal type

  • Naming and metadata corrections

  • Priority repair list