ESP32-C3 Multi-Board Design

flux

Work done
  • Updated the schematic into a dual-board stack concept: primary board keeps ESP32-C3, TMP117, LIS2DW12, and J8; secondary board carries LiPo charging/power, pogo access, external antenna interface, and J9/J10.
  • Added and wired the J8/J9 board-to-board interconnect and J10 U.FL antenna interface; core ERC checks are passing.
  • Reconfigured the PCB into a two-board 28 mm-wide stack/panel representation and re-placed the components into primary/secondary clusters.
  • Documented the partition, interconnect pinout, verification state, and manual-routing priorities in Two-Board Stack Revision.
Success criteria review
  • ✅ Dual-board partition defined and reflected in schematic/component roles.
  • ✅ Core functions preserved: ESP-NOW MCU, TMP117, LIS2DW12, LiPo charging/power, and pogo access remain connected.
  • ⚠️ Layout de-risked but not fully clean: missing footprints and ERC checks pass, but remaining physical-layout issues still need routing/layer cleanup before fabrication.
Next steps
  • Refresh/regenerate routing for the new two-board placement, then clear the remaining physical layout issues before manufacturing export.
Check DRC issues
Export assembly files
Show interconnect pinout
Document routing priorities
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  • Generic Inductor
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Thermal Accel Sensor

Thermal Accel Sensor thumbnail
Welcome to your new project. Imagine what you can build here.

Properties

Frozen for manual routing review

Manual routing review only; no schematic or PCB architecture changes intended

2026-04-29

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