ESP32-C3 Multi-Board Design

flux

  • Set Layout's sizeX to "28mm"
  • Set Layout's sizeY to "58mm"
  • Set Layout's boardShape to "=svgPath("M 0 0.0112 Q 0.014 0.0112 0.014 -0.0028 Q 0.014 -0.0168 0 -0.0168 Q -0.014 -0.0168 -0.014 -0.0028 Q -0.014 0.0112 0..."
  • Set Layout's stackup to "Standard 4 Layer (Custom)"
  • Set Layout's boardInsetMargin to "0.2mm"
  • Set Layout's keepOut to "0.2mm"

flux

Placed 36 component(s): C7, C1, J4, U2, C14, C2, C3, R4, C4, U1, L1, J9, C12, J6, C11, D1, R2, R7, R5, R3, J8, U4, J5, J3, R6, J7, C6, C5, J10, U5, J2, U3, F1, R1, J1, C13

flux

Work done
  • Updated the schematic into a dual-board stack concept: primary board keeps ESP32-C3, TMP117, LIS2DW12, and J8; secondary board carries LiPo charging/power, pogo access, external antenna interface, and J9/J10.
  • Added and wired the J8/J9 board-to-board interconnect and J10 U.FL antenna interface; core ERC checks are passing.
  • Reconfigured the PCB into a two-board 28 mm-wide stack/panel representation and re-placed the components into primary/secondary clusters.
  • Documented the partition, interconnect pinout, verification state, and manual-routing priorities in Two-Board Stack Revision.
Success criteria review
  • ✅ Dual-board partition defined and reflected in schematic/component roles.
  • ✅ Core functions preserved: ESP-NOW MCU, TMP117, LIS2DW12, LiPo charging/power, and pogo access remain connected.
  • ⚠️ Layout de-risked but not fully clean: missing footprints and ERC checks pass, but remaining physical-layout issues still need routing/layer cleanup before fabrication.
Next steps
  • Refresh/regenerate routing for the new two-board placement, then clear the remaining physical layout issues before manufacturing export.
Check DRC issues
Export assembly files
Show interconnect pinout
Document routing priorities
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Files

Schematic

Layout

3D View

Two-Board Stack Revision
Summary
The compact ESP32-C3 sensor node has been revised into a two-board stack concept. The primary board keeps the radio/MCU and local sensors. The secondary board carries battery, charging, regulation, pogo access, and external antenna interface hardware.
Partition
Primary sensor/MCU board
  • U1 ESP32-C3-MINI-1U-N4: ESP-NOW radio/MCU, external antenna-capable module.
  • U2 TMP117AIDRVR: contact temperature sensor, kept near thermal contact area and away from charger/regulator heat.
  • U3 LIS2DW12TR: motion sensing.
  • J8 BM23PF0.8-10DP-0.35V(51): primary board-to-board interconnect.
  • Local sensor/MCU passives remain with their ICs.
Secondary power/interface board
  • J9 BM23PF0.8-10DP-0.35V(51): secondary board-to-board interconnect, mates to J8.
  • U4 MCP73831T-2ATI/OT: LiPo charger.
  • U5 TPS63031DSKR: 3.3 V buck-boost regulator.
  • J1 SM02B-GHS-TB(LF)(SN): LiPo battery connector.
  • F1 0603L050YR and D1 USBLC6-2SC6: input protection/ESD support.
  • J2-J7: pogo/test pads for charging, UART/programming, EN, BOOT, and ground access.
  • J10 U.FL-R-SMT-1(10): secondary-board RF/mechanical antenna interface.
Board-to-board interconnect pinout

Table

PinNetFunction
1GNDReturn/reference
23V3Regulated output to primary board
3VBATBattery rail handoff
4POGO_5V_INCharging/programming 5 V input path
5UART_TX_MCUProgramming/communication UART TX
6UART_RX_MCUProgramming/communication UART RX
7ESP_ENReset/enable access
8BOOTBootloader strap access
9CHG_STATCharger status to MCU
10GNDReturn/reference
MP padsGNDMechanical shield/return
Layout changes
  • The physical layout is now represented as two 28 mm circular board outlines in one review layout, with overall width held to 28 mm.
  • A 6-layer stackup is currently applied for routing margin and return-path control in the dense stack representation.
  • Components were re-placed into primary/secondary clusters. U2 was kept in the primary thermal region; charger/regulator hardware was moved to the secondary cluster.
  • J8/J9 were placed near the stack centerline for mating. Pogo pads and J10 are edge-accessible on the secondary side.
Verification snapshot
  • Schematic ERC checks requested for floating pins, no-connects, single-pin nets, and undriven nets are passing.
  • Missing-footprint check is passing.
  • Known remaining layout issues after automated placement:
    • Invalid-layer checks remain active and appear tied to imported/generated layout nodes rather than missing schematic connectivity.
    • A small set of airwires remains after re-placement; these require routing cleanup.
    • Some copper overlap remains after re-placement; likely stale/old route geometry should be removed or regenerated during manual/auto routing.
Manual routing and manufacturing priorities
  1. Re-run/refresh routing after the two-board placement so stale route segments from the former single-board placement do not remain.
  2. Keep ESP32 external antenna/coax path short, referenced to ground, and clear of switching regulator copper.
  3. Preserve U2 thermal isolation from U4/U5/L1; avoid routing switching nodes or high-current battery paths under the TMP117 contact region.
  4. Route POGO_5V_IN, VBAT, 3V3, and GND with short/wide copper on the secondary board and across J8/J9.
  5. Keep UART_TX_MCU, UART_RX_MCU, ESP_EN, BOOT, and CHG_STAT low-speed but direct through the interconnect.
  6. Treat the current two-circle layout as a stack/panel representation; final fabrication should split the two 28 mm boards or use the manufacturer’s approved panelization method.

  • Summary

  • Partition

  • Primary sensor/MCU board

  • Secondary power/interface board

  • Board-to-board interconnect pinout

  • Layout changes

  • Verification snapshot

  • Manual routing and manufacturing priorities