The connectivity comparison confirms that all 49 nets still connect the same pins. The readability check found more work in the op-amp stages and electrode-jack wiring, which I’m correcting now.
The analog stages now have drawn signal paths, but a wire-placement bug on flipped symbols is blocking part of the USB drawing. I’ll leave the affected connections labeled and finish the independent label fixes; the bug needs Contact Support.
I arranged all 78 components into eight functional blocks and added local wires and net labels. All 49 nets retain exactly the same pin connections; no electrical connections changed.
The drawing is not fully clean: wire crossings and label crowding remain, and a flipped-symbol wire-placement bug blocks the shared USB power wire. That bug needs Contact Support; the remaining drafting cleanup is still open.
Implemented capture 07d2baa4, 2026-10-28: 71 components / 44 electrically connected nets. U3 AD8232ACPZ-RL provides a fixed-gain INA, servo high-pass, reference, postamp and driven reference. U4 MCP6002-E/SN implements two unity Sallen–Key sections. U1 STM32F401CEU6 records one differential surface-EMG channel.
Safety boundary
Electrode simulator only until qualified whole-system approval. No onboard isolation exists. External USB power and data isolation, shield, SWD, instruments, alternate returns, leakage and normal/single-fault behavior must be verified before any human connection. No medical compliance claim. J1 remains SJ-3524-SMT-TR: tip pin 2 positive, ring pin 3 negative, sleeve pin 1 driven reference never GND, switch pin 4 NC. No GPIO detection.
Design targets
Each signal leg: two 180 kΩ, 1%, 0402 resistors with midpoint clamp; 10 MΩ bias to VMID; 47 pF differential and 10 pF common-mode filtering.
Approximate 20–500 Hz acquisition band, not an exact production 500 Hz mask. Native behavioral peaks 96.587 / 484.834 V/V; −3.000 dB bands 19.817–497.715 / 19.814–497.658 Hz.
Driven reference: C30 = 10 nF, two 200 kΩ limiters, D5 at midpoint. Real-loop stability remains unvalidated despite bounded model margins.
Normal input 4.75–5.25 V, externally isolated; TPS7A2033 regulator and 10 Ω analog filter. The 60 mA design envelope is an assumption to verify.
All 26 ordinary resistors 0402. C1/C4/C5/C10/C11 remain 0603 pending effective-C/ESR qualification; F1 remains 0805 PPTC; C23 is the sourced stable 1206 exception.
Acceptance and release
Read-only pin/net/property verification and ERC completed: 0 errors / 1 existing D4 pin-type warning. Native behavioral AC/DC/linear transient and bounded analytical noise/alias/tolerance/RLD calculations are completed, not physical qualification. No official nonlinear AD8232 model was executed.
Release requires exact procurement/effective-C/derating/pad qualification; complete layout/routing/DRC; measured supply/inrush/load/thermal and reference behavior; all-node headroom and offset/artifact/open-lead recovery; complete noise/alias/ADC ENOB; switched ADC settling; actual RLD return ratio; defined-pulse ESD/backpower tests; qualified whole-system isolation/leakage/fault approval. Provisional ADC target: residual <0.25 LSB, about 195 µV at 3.2 V, by acquisition end without sustained ringing.
Simulation Guide contains all 71 parts, IC pin maps, equations, evidence and test conditions. Passive Package Qualification contains every resistor stress screen. No firmware or scripts are deliverables.