The connectivity comparison confirms that all 49 nets still connect the same pins. The readability check found more work in the op-amp stages and electrode-jack wiring, which I’m correcting now.
The analog stages now have drawn signal paths, but a wire-placement bug on flipped symbols is blocking part of the USB drawing. I’ll leave the affected connections labeled and finish the independent label fixes; the bug needs Contact Support.
I arranged all 78 components into eight functional blocks and added local wires and net labels. All 49 nets retain exactly the same pin connections; no electrical connections changed.
The drawing is not fully clean: wire crossings and label crowding remain, and a flipped-symbol wire-placement bug blocks the shared USB power wire. That bug needs Contact Support; the remaining drafting cleanup is still open.
The implemented AD8232ACPZ-RL / MCP6002-E/SN architecture has 71 components / 44 connected nets. AD8232 provides the fixed-gain INA, servo, reference, postamp and RLD; MCP6002 provides both unity Sallen–Key filters. STM32, USB-C, LDO, SWD and nominal 12 MHz crystal boundaries remain.
Critical details:
J1 SJ-3524-SMT-TR: tip pin 2 positive, ring pin 3 negative, sleeve pin 1 driven reference never GND, switch pin 4 NC. No GPIO detector.
Each signal has two 180 kΩ limiters; RLD has two 200 kΩ. Clamp midpoints retain a body-facing resistor to the jack. DC current limiting is not ESD or patient-safety certification.
R17 = 402 kΩ always remains feedback. J4 joins R19 = 100 kΩ to VMID only when shunted: postgain 1 / 5.02, nominal total 100 / 502.
R14/R15 and C22 filter REFIN. C22 is not REFOUT bypass. VMID fans to bias returns, J4 and SW. SW→VMID with FR low is a reviewed engineering interpretation, not a quoted unused-pin instruction. AC/DC low selects DC lead-off; its outputs are unused.
C24 and C26 are feedback capacitors to their corresponding filter outputs, not GND. LP2_B needs compact, clean layout because its 220 pF shunt is sensitive to input/board capacitance and leakage.
C30 = 10 nF is a concrete RLD bench default. Nominal modeled minimum phase margin is 55.33°, but real-loop stability and strong mains rejection are not established.
All 26 ordinary resistors are 0402. Retained bulk 0603 parts require exact effective-C/ESR qualification; no universal smaller-package unavailability is claimed. F1 is an 0805 PPTC.
Interpretation and gates
Behavioral nominal peaks are 96.587 / 484.834 V/V, approximately 19.8–498 Hz bandwidth. Settled ±300 mV electrode-offset capability is not fast-artifact headroom. MCP offsets can add about 9 mV under cited conditions; firmware subtraction cannot restore clipping. R1 inrush/short pulse, R24 fault stress, crystal CL, reference dynamics, ADC settling, real RLD, complete noise/alias, procurement and ESD/isolation remain gates.
The Simulation Guide has all values, pins and evidence. Minimal replacement placement is complete, not full-board routing or full schematic drafting. Electrode simulator only until qualified whole-system isolation/leakage/fault approval.