PCB Placement Groups
This file is the placement guide for the 80 mm, four-layer Smart Coaster PCB. Component IDs are always included. Items marked critical-close should be placed first and kept together; auxiliary items may be placed slightly farther away when necessary.
Top Layer
LED ring: LED1–LED24
Primary components: LED1, LED2, LED3, LED4, LED5, LED6, LED7, LED8, LED9, LED10, LED11, LED12, LED13, LED14, LED15, LED16, LED17, LED18, LED19, LED20, LED21, LED22, LED23, LED24.
Keep the physical order continuous around the ring: LED1 → LED2 → … → LED24.
Pair-local decoupling; place each capacitor between or immediately inboard of its associated pair:
- LED1–LED2: C6
- LED3–LED4: C7
- LED5–LED6: C8
- LED7–LED8: C9
- LED9–LED10: C10
- LED11–LED12: C11
- LED13–LED14: C12
- LED15–LED16: C13
- LED17–LED18: C14
- LED19–LED20: C15
- LED21–LED22: C16
- LED23–LED24: C17
Auxiliary LED-rail component: C5 is the bulk 5 V capacitor. Place C5 on Top, inboard of LED1 and LED24, and near U5 and R6. The 5 V source is the Bottom-side U3 output cluster—specifically U3, L1, C21, and C22—so the 5 V transition vias feeding the LED ring should be placed near C5 and the U3/L1/C21/C22 cluster.
MCU and radio: U1
Primary component: U1.
- Critical-close: C1, directly at U1 3V3/GND.
- Strapping and control: R2 at U1 GPIO2; R17 at U1 GPIO8.
- Bottom-side button interfaces: SW1/R1/C2 connect to U1 EN; SW2/R3 connect to U1 GPIO9.
- Preserve the U1 antenna copper/component keepout. Do not place components or stitching vias beneath the antenna section.
LED data level shifter: U5
Primary component: U5.
- Critical-close: C4 at U5 VCC/GND.
- Signal path: U1 IO10 → U5 → R6 → LED1.
- Keep U5, C4, and R6 together and reasonably close to U1 and LED1. R6 should sit near the U5 output or LED1 input.
Top-access test points
Keep these accessible rather than buried beneath large parts:
- TP1: 5V; associated with the U3/L1/C21/C22 5 V regulator output.
- TP2: GND; common factory-pogo ground reference.
- TP3: USB_D+; associated with U1, U6, and J4.
- TP4: USB_D−; associated with U1, U6, and J4.
- TP5: ESP_EN / reset
- TP6: GPIO9_BOOT
For fixture access, keep all six test points on Top and arrange them as one compact pogo-pad bank when practical. Keep TP3 and TP4 adjacent as the USB pair, TP5 and TP6 adjacent as the programming-control pair, and TP1 and TP2 adjacent as the power/reference pair. The bank should remain outside the U1 antenna keepout.
Silkscreen requirements for the test bank:
- Add a clear pin-1 marker beside TP1.
- Label the opposite endpoint TP6, so the fixture cannot be connected in reverse.
- Add a compact order legend: TP1 5V | TP2 GND | TP3 D+ | TP4 D− | TP5 EN | TP6 BOOT.
- Keep all test-bank silk clear of the pogo contact surfaces.
- If space is limited, the minimum required markings are the TP1/pin-1 marker, TP6, and an orientation arrow from TP1 → TP6.
Bottom Layer
Trunk power and CAN connector: J1
Primary component: J1.
- Power-entry critical-close: F1 immediately downstream of J1 12V_RAW; D1 from 12V_PROT to GND.
- CAN critical-close: U2 near J1 CANH/CANL; C3 directly at U2 VCC/GND.
- General proximity: U3 power stage receives the protected 12 V output from F1/D1.
Preferred signal/power flow: J1 → F1/D1 → U3, while J1 CANH/CANL route directly to U2.
12 V to 5 V buck stage: U3
Primary component: U3.
- Critical input loop: C18, C19 at U3 VIN/GND.
- Critical switching loop: C20 between U3 BOOT and SW; L1 directly at U3 SW.
- Critical output loop: C21, C22 from the L1/5V output to GND.
- Feedback: R11 and R12 at U3 FB; keep the feedback node away from U3 SW and L1.
Complete cluster: U3, L1, C18, C19, C20, C21, C22, R11, R12.
5 V to 3.3 V buck stage: U4
Primary component: U4. This stage should ultimately be grouped on Bottom using the same short-loop principles as U3.
- Critical input loop: C23, C24 at U4 VIN/GND.
- Internal VCC bypass: C26 at U4 VCC/GND.
- Critical switching loop: C25 between U4 BOOT and SW; L2 directly at U4 SW.
- Critical output loop: C27, C28 from the L2/3V3 output to GND.
- Feedback: R14 and R15 at U4 FB.
- Power-good: R16 near U4 PG.
Complete cluster: U4, L2, C23, C24, C25, C26, C27, C28, R14, R15, R16.
Load-cell connector and ADC: J2 / U8
Primary components: J2, U8.
- Connector-entry critical-close: R18, R19, C32.
- Place in signal order: J2 → R18/R19/C32 → U8.
- U8 supply/bypass critical-close: C29, C30, C31.
- Reference filter critical-close: R20, R21, C33.
- Auxiliary: R17 is the U1 GPIO8 pull-up and does not need to be directly beside J2.
Complete cluster: J2, U8, R18, R19, R20, R21, C29, C30, C31, C32, C33.
Pump connector and switch: J3 / Q1
Primary components: J3, Q1.
- Critical current loop: J3, Q1, D2.
- Gate network critical-close: R7 and R8 immediately beside Q1.
- Place D2 close to J3/Q1 to minimize the flyback-current loop.
Complete cluster: J3, Q1, D2, R7, R8.
USB-C connector: J4
Primary component: J4.
- Data-path critical-close: U6 immediately beside J4, between J4 and U1.
- CC resistors: R9 at J4 CC1; R10 at J4 CC2.
- VBUS power path: U7 close to J4 VBUS.
- Keep USB D+ and D− short, parallel, and direct through U6 toward U1.
Complete cluster: J4, U6, U7, R9, R10.
Note: C14 and C16 belong to LED-pair decoupling and are not USB support parts, even if they appear near J4 during temporary placement.
Reset button: SW1
Primary component: SW1.
- Critical-close: R1 and C2.
- Signal relationship: U1 EN ↔ R1/C2/SW1.
- Auxiliary accessible point: TP5.
Complete cluster: SW1, R1, C2; keep TP5 accessible nearby when practical.
Boot button: SW2
Primary component: SW2.
- Critical-close: R3.
- Signal relationship: U1 GPIO9 ↔ R3/SW2.
- Auxiliary accessible point: TP6.
Complete cluster: SW2, R3; keep TP6 accessible nearby when practical.
Placement Priority
- Preserve the fixed LED ring, U1 antenna keepout, mounting holes, and connector access.
- Place the U3 and U4 power-stage loops tightly.
- Place connector protection and interface clusters beside J1–J4.
- Place C1, C3, C4, C18–C31 and other IC-local capacitors at their parent power pins.
- Place feedback, pull-up, gate, and series resistors after the parent ICs and connectors are fixed.
- Keep test points accessible and move silkscreen only after electrical placement is stable.