Nixie Tube Decade Counter Setup
1:38
General
Chat History
Project
Knowledge Base
Plan
TC
Planning component linking.
Querying design details.
Clarifying countdown needs.
Implementing Nixie countdown.
Creating a plan for integration.
Using Knowledge Base Tool.
Planning connections and components.
I’ll integrate a CD4017 decade counter clocked by your 555 for the Nixie countdown.
- Add CD4017 with 100 nF decoupling; power from VCC/GND.
- Route IC1:Q through U2 to CD4017 CLK; add a 3-pin AUTO/STEP clock-select header.
- Add debounced STEP via spare U2 channel; add RESET pull-up/header to CD4017 RST.
- Break out Q0–Q9 to a header; for countdown wire Q0->digit 9 … Q9->digit 0.
- Verify VCC: if >6 V, avoid 74HC14 to VCC; use a CD40106B buffer. If 3.3 V logic is used, switch to a CMOS 555 per best practice.
Click Start on the plan bar to run this. Quick checks:
- What is VCC?
- Do you want Q0–Q9 on a 2×6 or 1×12 header?
- Keep the AUTO/STEP via jumper-select, or prefer diode-OR so both are always available?
22 days
1:21
General
Chat History
Project
Plan
TC
Planning circuit steps.
Defining pinout for connections.
Adding debounced components.
Integrating debounce components.
Planning debouncing and reset.
Goal acknowledged: integrate a 5 V 555‑clocked CD4017 with AUTO/STEP, RESET, and a 2×6 outputs header.
Plan:
- Clock: Keep IC1 with R4/TC; add 100 nF decouplers at IC1/U2/U3.
- Conditioning + select: Route IC1:Q through U2 to U3 CLK; optional 100 Ω series; add Pin Header 01x03 2.54mm AUTO/STEP with center to CLK.
- STEP: Add debounced pushbutton via spare U2 gate to STEP side of selector; use 10kΩ Resistor + 100nF Capacitor.
- RESET: Add pull network per CD4017 datasheet and Pin Header 01x02 2.54mm to U3 RESET.
- Outputs: Place Pin Header 02x06 2.54mm for Q0–Q9 plus GND and VCC.
Click Start on the plan bar to run this.
Choose output header pinout
Find 2x6 header part
Debounce values decision
Reset behavior choice
Clock range target
22 days
Plan completed.
Show Plan
R1
Resistance
51k Ω
GND
VCC
R5
Resistance
100Ω
GND
IC1 TR - IC1 THR
U3 CLOCK - J2 P1
IC1 TR - IC1 THR
R3
Resistance
10k Ω
VCC
R2
Resistance
51k Ω
VCC
VCC
VCC
VCC
IC1
TC
Capacitance
74u F
RTH
J1
VCC
LED1
CLK
Reviews
Electrical Rule Checks
Duplicate Designators
Reports components with identical designators.
No-Connect Violation
Reports no-connect pins that are connected.
Missing Power • 3
Component | |
|---|---|
Single Pin Nets • 1
Component | |
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Missing Designator
Reports components without a designator.
Design Rule Checks
Overlapping Copper • 9
Invalid Layer
Reports nodes that are assigned to a layer that doesn't exist in the layout stackup.
Component Overrides
Reports components that have been modified using the "!important" flag.
Airwires • 27
Designators | Net | |
|---|---|---|
Layers with Multiple Fills
Reports layers that have multiple copper fills of different nets. Make sure the Connected Layers rule value of nets with fills is valid.
Floating Copper • 1
Name | |
|---|---|
Protected Intrusions
Reports intrusions from objects of other nets into polygons or fills that have the Protected layout rule applied.
Missing Footprints
Reports components that need a footprint but don't have one.
System Checks
Auto-Layout
BetaReports issues with Auto-Layout if Flux cannot route something or must ignore a configuration.
Passive Components
Resistor Power Rating
BetaChecks that the power traveling across a given resistor is under its rating with 50% headroom.
Learn morePull Up/Pull Down Presence
BetaChecks that IC pins that require pull up or pull down resistors have them.
Learn moreCapacitor Voltage Rating
BetaChecks that capacitors have appropriate voltage ratings to prevent overheating and ensure reliable circuit operation.
- Wirelessly connects nets on schematic. Used to organize schematics and separate functional blocks. To wirelessly connect net portals, give them same designator. #portaljharwinbarrozo43.0M
- Wirelessly connects power nets on schematic. Identical to the net portal, but with a power symbol. Used to organize schematics and separate functional blocks. To wirelessly connect power net portals, give them the same designator. #portal #powerjharwinbarrozo11.4M
- A generic fixed resistor for rapid developing circuit topology. Save precious design time by seamlessly add more information to this part (value, footprint, etc.) as it becomes available. Standard resistor values: 1.0Ω 10Ω 100Ω 1.0kΩ 10kΩ 100kΩ 1.0MΩ 1.1Ω 11Ω 110Ω 1.1kΩ 11kΩ 110kΩ 1.1MΩ 1.2Ω 12Ω 120Ω 1.2kΩ 12kΩ 120kΩ 1.2MΩ 1.3Ω 13Ω 130Ω 1.3kΩ 13kΩ 130kΩ 1.3MΩ 1.5Ω 15Ω 150Ω 1.5kΩ 15kΩ 150kΩ 1.5MΩ 1.6Ω 16Ω 160Ω 1.6kΩ 16kΩ 160kΩ 1.6MΩ 1.8Ω 18Ω 180Ω 1.8KΩ 18kΩ 180kΩ 1.8MΩ 2.0Ω 20Ω 200Ω 2.0kΩ 20kΩ 200kΩ 2.0MΩ 2.2Ω 22Ω 220Ω 2.2kΩ 22kΩ 220kΩ 2.2MΩ 2.4Ω 24Ω 240Ω 2.4kΩ 24kΩ 240kΩ 2.4MΩ 2.7Ω 27Ω 270Ω 2.7kΩ 27kΩ 270kΩ 2.7MΩ 3.0Ω 30Ω 300Ω 3.0KΩ 30KΩ 300KΩ 3.0MΩ 3.3Ω 33Ω 330Ω 3.3kΩ 33kΩ 330kΩ 3.3MΩ 3.6Ω 36Ω 360Ω 3.6kΩ 36kΩ 360kΩ 3.6MΩ 3.9Ω 39Ω 390Ω 3.9kΩ 39kΩ 390kΩ 3.9MΩ 4.3Ω 43Ω 430Ω 4.3kΩ 43KΩ 430KΩ 4.3MΩ 4.7Ω 47Ω 470Ω 4.7kΩ 47kΩ 470kΩ 4.7MΩ 5.1Ω 51Ω 510Ω 5.1kΩ 51kΩ 510kΩ 5.1MΩ 5.6Ω 56Ω 560Ω 5.6kΩ 56kΩ 560kΩ 5.6MΩ 6.2Ω 62Ω 620Ω 6.2kΩ 62KΩ 620KΩ 6.2MΩ 6.8Ω 68Ω 680Ω 6.8kΩ 68kΩ 680kΩ 6.8MΩ 7.5Ω 75Ω 750Ω 7.5kΩ 75kΩ 750kΩ 7.5MΩ 8.2Ω 82Ω 820Ω 8.2kΩ 82kΩ 820kΩ 8.2MΩ 9.1Ω 91Ω 910Ω 9.1kΩ 91kΩ 910kΩ 9.1MΩ #generics #CommonPartsLibraryjharwinbarrozo1.5M
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Inspect
555 Circuit
Controls
Properties
System Architecture
```mermaid
flowchart TD
subgraph AST [Astable]
NE555["NE555 Astable"]
R1["R1"]
R2["R2"]
TC["TC"]
POT["Trimpot"]
end
subgraph PWR [Power]
VCC["VCC"]
GND["GND"]
DCAP["Decoupling Caps"]
end
subgraph OUT [Clock Output]
RES["Series Resistor"]
BUF["Schmitt Trigger"]
COH["CLOCK OUT\nHeader"]
end
subgraph RSTSTEP [Reset/Step Input]
RPU["Reset Pull-up"]
RSH["RESET/STEP\nHeader"]
SB["STEP Button"]
RC["RC Debounce"]
end
DC["Decade Counter"]
VCC --> DCAP
GND --> DCAP
VCC --> NE555
GND --> NE555
NE555 --> R1
NE555 --> R2
NE555 --> TC
NE555 --> POT
NE555 --> RES
RES --> BUF
BUF --> COH
COH --> DC
RPU --> RSH
RSH --> NE555
SB --> RC
RC --> NE555
RSH --> DC
```
Availability & Pricing
| Distributor | Qty 1 | |
|---|---|---|
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