Build Instructions for Low-Fi Synth
2:15
Gathering resistor divider info.
Clarifying CV input design.
Using knowledge tools for design.
Gathering component specifications.
Accessing knowledge base.
Calculating.
Calculating.
Calculating.
Calculating.
Designing diode clamp protections.
Great—let’s size a CV input attenuator with rail clamps that guarantees the protected node stays within 0–VCC.
Please confirm:
- What is VCC on this board (5 V, 9 V, or other)?
- Expected external CV range to accept (e.g., 0–10 V, ±5 V, up to ±12 V)?
- Any target input impedance (common: ≥100 kΩ)?
Connection recipe
- From CV jack tip: series Resistor Rin -> divider top (Rtop).
- Divider: Rtop to jack side, Rbot to GND; protected node is the Rtop/Rbot junction -> goes to the control pin.
- Clamp diodes at the protected node: one Schottky Diode to VCC (anode at node, cathode at VCC) and one to GND (cathode at node, anode at GND).
- Optional robustness: add a jack-side TVS Diode and/or a series PTC Resettable Fuse for abuse/ESD.
How to size
- Divider ratio: Vnode_max = Vin_max × Rbot/(Rtop+Rbot) ≤ VCC. Pick Rbot and solve Rtop = Rbot × (1/(Vnode_max/Vin_max) - 1).
- Series resistor Rin limits clamp current under over/under-voltage. Use Iclamp = (Vin - (rail + Vf)) / Rin and keep it below the IC pin injection spec. As a conservative design target before picking exact parts, cap Schottky current to ≈2 mA and update once the IC and diode datasheets are locked.
- Precision: if CV scaling accuracy matters, use 1% or better resistors (0.1% for tight tracking).
Two ready-to-use examples
Example A: Accept 0–10 V CV, protect to VCC = 5 V, survive up to ±12 V on the jack
- Divider: make 10 V -> 5 V, so 0.5 ratio. Use Rtop = 100 kΩ, Rbot = 100 kΩ (input Z ≈ 200 kΩ).
- Series resistor for clamps (target 2 mA, assume Schottky Vf ≈ 0.3 V):
- High-side worst case (Vin = +12 V): Rin ≥ (12 - (5 + 0.3)) / 0.002 = 3350 Ω → choose 4.7 kΩ or 10 kΩ for margin.
- Low-side worst case (Vin = -12 V): Rin ≥ (12 - 0.3) / 0.002 = 5850 Ω → choose 10 kΩ.
- Pick Rin = 10 kΩ. Parts: Resistor, Schottky Diode.
Example B: Accept 0–10 V CV, protect to VCC = 9 V, survive up to ±12 V
- Divider: 10 V -> 9 V (ratio 0.9). With Rbot = 100 kΩ:
- Rtop = 100000 × (1/0.9 - 1) = 11111 Ω → use 11.0 kΩ (E24) or 11.3 kΩ (E96).
- Series resistor for clamps (2 mA, Vf ≈ 0.3 V):
- High-side (Vin = +12 V): Rin ≥ (12 - (9 + 0.3)) / 0.002 = 1350 Ω → choose ≥1.8 kΩ.
- Low-side (Vin = -12 V): Rin ≥ 5850 Ω → choose 10 kΩ.
- Pick Rin = 10 kΩ. Parts: Resistor, Schottky Diode.
Notes
- The series resistor sizing method ensures clamp current I = (Vin - rail - Vf)/Rin stays within the device’s injection rating; finalize Rin after we check the IC and diode datasheets.
- Very high divider values increase impedance and noise pickup; 100 kΩ class is a good starting point for CV.
- Add a small RC (e.g., 100–220 pF from node to GND) if you need to tame HF spikes into the control pin.
Want me to lock values for your exact VCC and CV range and add the input to the project?
60 days
0:52
Planning the Atari Punk Console.
Starting your APC plan now. We’ll:
- Add the dual 556‑type APC core, power (9V battery + 5–12V DC jack with auto battery disconnect), and decoupling.
- Wire three board‑mounted pots (Frequency, Pulse Width, Volume).
- Implement CV input with divider, series resistor, and 0–VCC rail clamps to a 1/4" jack.
- Build AC‑coupled audio out to a 1/4" jack, optional buffer.
- Label, connect, run ERC/DRC, and prep exports.
Click Start on the plan bar to execute.
Plan
- Design a board‑mounted Atari Punk Console (APC) with a low‑power dual CMOS timer core (556‑type), dual power input (9V battery and 5–12V center‑negative DC jack with automatic battery disconnect), CV input clamped to 0–VCC, three board‑mounted pots for Frequency, Pulse Width, and Volume control, and 1/4" mono jacks for Audio Out and CV In. The design should be optimized for deeper bass and finer pitch steps.
#Implementation plan
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APC Core Setup
- Select and add a low‑power dual CMOS timer (556‑type) to serve as the APC oscillator core.
- Configure dual oscillator outputs, tailoring for deeper bass and finer duty cycle adjustments using the Frequency and Pulse Width controls.
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Power Subsystem Implementation
- Add a 9V battery header and a 5–12V center‑negative DC jack with a jack‑switch mechanism for battery auto‑disconnect.
- Implement polarity and ESD protection along with proper decoupling capacitors for the VCC rail.
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Board‑Mounted Controls and Connections
- Add three board‑mounted potentiometers for Frequency, Pulse Width, and Volume control.
- Route each control path to the corresponding control node in the APC core.
-
CV Input Circuitry
- Design a CV input circuit that clamps the incoming signal to the 0–VCC range.
- Utilize resistor networks, series resistors, and clamping diodes to ensure proper voltage limitation.
- Connect to the designated 1/4" mono jack for CV In.
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Audio Output Path
- Develop the audio output path including an AC‑coupling stage and integration with the Volume pot.
- Optionally include a buffer to drive the 1/4" mono Audio Out jack.
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Review and Labeling
- Verify all schematic connections against ERC/DRC standards.
- Clearly label all nets, control points, and header/jack assignments.
- Prepare manufacturing exports once schematic and PCB layout are completed.
#Success criteria
- The APC core oscillates with deeper bass and offers finer pitch control.
- Dual power inputs work reliably with automatic battery disconnect via the jack switch.
- The CV input is correctly clamped to 0–VCC and functions with sequencers/LFOs.
- All board‑mounted pots and jacks are properly connected and labeled.
- Schematic and PCB layout pass ERC/DRC checks and are ready for manufacturing exports.
Pick the 556 IC
Define VCC choice
Choose pots and jacks
Implement CV clamp
Audio out stage
60 days
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