Smart Relay Logic Board Design
Execution stopped due to insufficient credits.
1:06
Working.
Started: Cleaning invalid-layer traces and layout rules
Working.
Updated 4 layout rules
0:03
Set Layout's minTraceWidth to "0.20mm"
Set Layout's traceWidth to "0.25mm"
Set Layout's keepOut to "0.20mm"
Set Layout's boardInsetMargin to "0.25mm"
0:00
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