Refine this doc

Ask about this doc

TLC555CDR Part Audit

Sources

Existing part Datasheet URL: https://storage.googleapis.com/graviton-electric-symbols/document_assets/user-uploaded/06260e592dbd7a4e4a2deda7a6e4aa66ecfc39f3b5512968a5710b01600b29de.pdf
Official manufacturer datasheet located: https://www.ti.com/lit/ds/symlink/tlc555.pdf
TI orderable-device page: https://www.ti.com/product/TLC555/part-details/TLC555CDR
Datasheet revision reviewed: SLFS043K, revised January 2026.

The part already had a Datasheet URL, so no Datasheet property change was required.

Metadata Review

Table

Item	Current part	TI source	Result
MPN	TLC555CDR	TLC555CDR	Match
Manufacturer	Texas Instruments	Texas Instruments	Match
Package	8-SOIC	SOIC (D), 8 pins; drawing D0008A; JEDEC MS-012 AA	Functionally correct, but current package text is less precise
Pin count	8	8	Match
Designator prefix	IC	Integrated circuit	Acceptable
Description	`TLC555CDR, Timer 2MHz, 2 ??? 15 V, 8-Pin SOIC-8`	CMOS timer, up to 2.1 MHz, 2 V to 15 V for TLC555C	Mismatch/formatting issue: corrupted voltage separator and rounded-down frequency

Symbol and Pin Cross-Check

All eight pin numbers and names match TI's top-view pinout:

Table

Pin	Symbol name	TI name	TI function/type	Result
1	GND	GND	Ground	Match
2	TRIG	TRIG	Input; starts timing when TRIG < 1/2 CONT	Match
3	OUT	OUT	High-current timer output	Match
4	RESET	RESET	Active-low reset input	Match
5	CONT	CONT	Comparator threshold control / bypass node	Match
6	THRES	THRES	End-of-timing comparator input	Match
7	DISCH	DISCH	Open-collector timing-capacitor discharge output	Match
8	VDD	VDD	Power supply	Match

Symbol mismatches

Every terminal currently has Pin Type = Unspecified; TI defines pins 2, 4, 5, and 6 as inputs, pins 3 and 7 as outputs, pin 1 as ground, and pin 8 as power supply.
Pin Description fields are absent. The symbol names and numbers are correct, but the requested descriptive metadata has not been populated.
The symbol layout is nonstandard visually: GND and OUT are on the left while VDD is on the right rather than power pins being top/bottom. This is cosmetic and does not alter electrical correctness.

Footprint Cross-Check

Current footprint asset: SOIC127P600X175-8N.kicad_mod.

TI D0008A recommended land pattern:

Current footprint geometry from the source asset:

Footprint result

Pad count, numbering sequence, pitch, body outline, row spacing, and pin-1 identification match the TI D-package geometry.
Pad dimensions differ slightly from TI's example land pattern: current 0.65 × 1.528 mm versus TI 0.60 × 1.55 mm. This is a small IPC-style variation and remains compatible with the lead dimensions; it is not considered a blocking footprint defect.
The footprint is suitable for TLC555CDR. No pad override or quality escalation is warranted from the reviewed geometry.

Key Specifications

Device: CMOS 555-compatible timer
Recommended supply range for TLC555C: 2 V to 15 V
Absolute maximum VDD: 18 V
Maximum astable frequency: 2.1 MHz typical under TI test conditions
Supply current: 180 µA typical at 5 V; 235 µA typical at 15 V
Output capability: 100 mA sink typical, 10 mA source typical
Absolute current limits: 150 mA sink, 15 mA source
Output rise/fall time at 5 V: 20 ns / 15 ns typical
TLC555CDR operating temperature: 0°C to 70°C
Package: 8-pin SOIC, TI code D, drawing D0008A, tape-and-reel orderable suffix R
Lifecycle: Active per TI product page

Recommended Corrections

Correct the description to: TLC555CDR CMOS timer, 2 V to 15 V, up to 2.1 MHz, SOIC-8 (D).
Populate electrical pin types for all eight terminals.
Add TI-derived Pin Description metadata for every terminal.
Optionally make the package property more precise: SOIC-8 (D), D0008A, JEDEC MS-012 AA.
Optionally replace the uploaded Datasheet URL with TI's stable official URL for provenance, although the existing property is populated and readable.

Reviews