Revisione Progetto PCB
Task unable_to_complete.
2:05
Started: rewiring replacement pads to original nets
Analyzing the schematic.
Running design review.
Analyzing the schematic.
Updated 4 connections
0:06
Connected SW1:1 to ^BAT
Connected SW1:2 to ^BAT_SW
Connected SW2:1 to ^BTN_PD2
Connected SW2:2 to ^GND
nets {
net GND = U1 GND_2 - U1 GND_3:GND, GND:GND, SW2:2, R7 P2 - U3 CE:GND, U3:CE, U4:2, J1:P2, J3:2, J4:GND_2, J4:GND_3, J4:GND_4, J4 GND_4 - D1 A:GND, U2:GND, J2:1, D1:A, R6:P2, D3 K - D4 K:GND, D4:K, C3:P2, U3:GND, U3:TEMP, C4:P2, U1:PC2_(ADC2/PCINT10), D3:K, R5:P2, J4:GND_1, C1:P2, U1:GND_3, U1:(PCINT20/XCK/T0)_PD4, U3:EP, R7:P2, C2:P2, U1:GND_1, U1:GND_2, D2:K, C5:P2;
net STDBY = R9:P2, D4:A, U3:~{STDBY};
net 3V3 = U1:AVCC, C1:P1, J3:6, C3:P1, R9:P1, J2:2, R2:P1, U1:VCC_2, U1:VCC_1, U4:1, U2:VOUT, R1:P1, R3:P1, R8:P1;
net USB_VBUS = C4:P1, D1:K, U3:VCC, J4:VBUS_4, J4:VBUS_3, J4:VBUS_2, J4:VBUS_1;
net CHRG = U3:~{CHRG}, R8:P2, D3:A;
net BAT = J1:P1, SW1:1, U3:BAT, U2:VIN, C5:P1;
net CHG_PROG = U3:PROG, R7:P1;
net BTN_PD2 = SW2:1, U1:PD2_(INT0/PCINT18);
net BAT_SW = SW1:2;
}
0:03
Welcome 👋
Flux helps you build PCBs faster with an AI teammate!
Create your account to collaborate, stay updated, fork your own version, and get instant answers from our AI agent.