#Goal

- Prepare targeted schematic edits to fix net and connectivity issues including unifying duplicate nets, separating and rewiring UART connections with series resistors and TVS protection, and updating the triac channel connection. Then run an Electrical Rules Check (ERC) to verify the changes.

#Implementation plan

1. Unify and clean net definitions:

1. Identify and merge duplicated nets (Dwin_Uart_Arduino, AC_HOT_IN, GND).

2. Remove empty duplicate nets for Q1_GATE_DRV and Q2_GATE_DRV.

2. Rewire UART signals:

1. Separate the unified UART net into two distinct nets, UART_TX and UART_RX.

2. Connect J4:PIN_3 to UART_TX and J4:PIN_4 to UART_RX.

3. Maintain R1 in series with UART_TX and R2 in series with UART_RX.

4. Connect TVS U9 across both UART_RX and UART_TX lines.

3. Complete the triac channel connection:

1. Connect Q4:A2 to the intended harness/output net ensuring it matches naming of other channels.

4. Normalize net properties:

1. Set UART_TX and UART_RX nets to the signal net class.

2. Ensure power nets (+5V and AC_HOT_IN) are correctly typed as power nets with proper voltage annotations.

5. Run ERC:

1. Execute the ERC on the updated schematic.

2. Review and report any remaining ERC issues.

#Success criteria

- All duplicate and empty nets are merged or removed accordingly.

- UART TX and RX signals are properly separated, connected, and include series resistors and TVS protection as required.

- Q4:A2 is correctly connected to the designated harness/output net.

- Net properties are normalized for both signal and power nets.

- ERC passes or clearly identifies any remaining issues for further refinement.