ESC Tasarım Detayları

avxp

PART 1/2 - İLK BATCH UYGULA Komut çok uzun olduğu için 2 parçaya bölüyorum.

🚀 PART 1: Ground Split + Buck Fix + 48V Short Düzeltmesi Bu adımları şimdi uygula: ✅ 1. R22'yi SİL (duplicate star-tie)

✅ 2. PGND Net Oluştur ve Bağla:

J1 PIN2
U1 pin3 (GND)
C1 negative (-)
C2 negative (-)
C3 negative (-)
C4 negative (-)
C5 negative (-)
C30 negative (-)
C31 negative (-)
D1 cathode (pin 2)
IC1 pin28 (PGND)
U4 pin2 (shunt negative)
U5 pin2 (shunt negative)
U6 pin2 (shunt negative)
IC1 SN1 (pin 23)
IC1 SN2 (pin 21)
IC1 SN3 (pin 19)
Q2 Source (via U4)
Q4 Source (via U5)
Q6 Source (via U6)
R1 pin1 (P1) ⭐ STAR POINT INPUT

✅ 3. GND Net Oluştur ve Bağla:

U3 pin1 (GND)
C6 negative (-)
C7 negative (-)
C8 negative (-)
U2 pin19 (VSS)
U2 pin28 (VSS)
U2 pin9 (VSSA)
C12 negative (-)
C13 negative (-)
C14 negative (-)
C15 negative (-)
C16 negative (-)
C17 negative (-)
C27 negative (-)
IC1 pin27 (AGND)
C28 negative (-)
C29 negative (-)
C18 negative (-)
C19 negative (-)
C20 negative (-)
C24 negative (-)
C25 negative (-)
C26 negative (-)
C21 negative (-)
J2 pin5 (SWD GND)
R1 pin2 (P2) ⭐ STAR POINT OUTPUT

✅ 4. R1 Star Point Verify:

R1 P1 → PGND net'inde mi? (kontrol et)
R1 P2 → GND net'inde mi? (kontrol et)
İki farklı net olmalı!

✅ 5. SW_NODE Oluştur (Yeni Net):

U1 pin2 (OUTPUT)
L2 P1
D1 pin1 (anode)

✅ 6. +5V Net Düzelt:

L2 P2
C5 positive (+)
C30 positive (+)
C31 positive (+)
U3 pin3 (VIN)
IC1 GVDD (pin X - datasheet kontrol)

✅ 7. +48V_BUS Net Düzelt (J1 PIN2'yi ÇIKAR!):

L1 P2
U1 pin1 (VIN)
C1 positive (+)
C2 positive (+)
C3 positive (+)
C4 positive (+)
Q1 Drain
Q3 Drain
Q5 Drain
IC1 pin42 (PVDD)
IC1 VDRAIN (pin X - eğer varsa)

✅ PART 1 TAMAMLANINCA: ERC'yi çalıştır ve kontrol et:

L2 short'u düzeldi mi? 48V-to-GND short'u kayboldu mu? PGND ve GND ayrı netler mi?

Sonucu paylaş, sonra PART 2'ye geçeceğiz!

⚡ PART 1'İ ŞİMDİ UYGULA! 🚀

28 days

flux

0:14

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28 days

Plan completed.

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Reviews

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Inspect

ten

Controls

Properties

Layout Notes

- Place [IC1](https://www.flux.ai/:handle/:documentSlug?fit=IC1) + power stage loop compact: +48V_BUS -> FETs -> shunts ([U4](https://www.flux.ai/:handle/:documentSlug?fit=U4), [U5](https://www.flux.ai/:handle/:documentSlug?fit=U5), [U6](https://www.flux.ai/:handle/:documentSlug?fit=U6)) -> PGND. Keep high di/dt copper short and wide.
- Keep [R1](https://www.flux.ai/:handle/:documentSlug?fit=R1) as the ONLY PGND<->GND star tie, placed adjacent to shunt cluster.
- Route CSA Kelvin pairs from shunts to [IC1](https://www.flux.ai/:handle/:documentSlug?fit=IC1) (SPx/SNx) as tight pairs, away from switch node/phase copper.
- Buck SW node (SW_BUCK net: [U1](https://www.flux.ai/:handle/:documentSlug?fit=U1) OUT, [L2](https://www.flux.ai/:handle/:documentSlug?fit=L2) P1, [D1](https://www.flux.ai/:handle/:documentSlug?fit=D1) pin1) keep copper small; place [D1](https://www.flux.ai/:handle/:documentSlug?fit=D1) and [C4](https://www.flux.ai/:handle/:documentSlug?fit=C4)/[C5](https://www.flux.ai/:handle/:documentSlug?fit=C5) close to [U1](https://www.flux.ai/:handle/:documentSlug?fit=U1).
- Decouplers: place [C28](https://www.flux.ai/:handle/:documentSlug?fit=C28)/[C29](https://www.flux.ai/:handle/:documentSlug?fit=C29) at [IC1](https://www.flux.ai/:handle/:documentSlug?fit=IC1) DVDD/AVDD; place MCU [C20](https://www.flux.ai/:handle/:documentSlug?fit=C20), [C18](https://www.flux.ai/:handle/:documentSlug?fit=C18), [C21](https://www.flux.ai/:handle/:documentSlug?fit=C21), [C22](https://www.flux.ai/:handle/:documentSlug?fit=C22), [C19](https://www.flux.ai/:handle/:documentSlug?fit=C19) at each VDD pin.
- Gate resistors ([R2](https://www.flux.ai/:handle/:documentSlug?fit=R2), [R3](https://www.flux.ai/:handle/:documentSlug?fit=R3), [R4](https://www.flux.ai/:handle/:documentSlug?fit=R4), [R5](https://www.flux.ai/:handle/:documentSlug?fit=R5), [R6](https://www.flux.ai/:handle/:documentSlug?fit=R6), [R7](https://www.flux.ai/:handle/:documentSlug?fit=R7)) must be within <5 mm of each MOSFET gate; keep gate drive loops short.
- Motor phases: keep PHASE_A/B/C copper wide and symmetric to [J3](https://www.flux.ai/:handle/:documentSlug?fit=J3).

System Architecture

```mermaid
flowchart TD
    subgraph Power_Entry_Filter [Power Entry/Filter]
        J48["48V Input Connector"] -->|+48V_IN| F1["Fuse"] --> L1["Input Filter Inductor"] -->|+48V_BUS| BUS["48V Bus"]
        BUS --> D_TVS["TVS to PGND"]
        BUS --> CIN_BULK["Bulk Cap 63V"]
        BUS --> CIN_MLCC1["1uF 100V"]
        BUS --> CIN_MLCC2["100nF 100V"]
    end
    subgraph DCDC [DC-DC]
        BUS --> BUCK["48V to 5V Buck"] -->|+5V| V5["5V Rail"]
        BUCK --> LBUCK["Buck Inductor"] --> V5
        BUCK --> DFREE["Freewheel Diode or Sync FET"] --> PGND
        V5 --> LDO["5V to 3.3V LDO"] -->|+3.3V| V33["3.3V Rail"]
    end
    subgraph Power_Stage [3-Phase Power Stage]
        BUS --> HS["3x High Side FET"] -->|PHASE_A/B/C| LS["3x Low Side FET"] --> SHUNT["Shunt"] --> PGND
        DRIVER["3-Phase Gate Driver"] --> HS
        DRIVER --> LS
        DRIVER --> BST["Bootstrap Diodes/Caps"]
        MTR["3-Pin Motor Connector"] -->|PHASE_A/B/C| HS
    end
    subgraph MCU [MCU]
        V33 --> MCU_IC["STM32G431CBT6"]
        MCU_IC --> SWD["5-Pin SWD"]
        MCU_IC -->|PWM| DRIVER
    end
    subgraph Current_Measurement [Current Measurement/Feedback]
        SHUNT --> CSA["Current Sense Amplifier"] -->|ADC| MCU_IC
    end
    subgraph Grounding [Grounding]
        PGND --> STAR["Star point near shunt"] --> GND
    end
```

Availability & Pricing

Distributor		Qty 1
	Arrow	$14.32–$16.25
	Digi-Key	$17.32–$17.67
	LCSC	$26.83–$27.03
	Mouser	$44.16
	TME	$20.49
	Verical	$4.34–$9.67

Assets

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