Building SCADA Sensor Node

Thought

Work done

Audited the current project state and confirmed the schematic still contains the core mixed-signal path around U2, U4, U7, U3, the Heltec headers J_HELTEC_L / J_HELTEC_R, relay connectors J_RELAY1 to J_RELAY6, fuse holders FH1 to FH6, CT inputs J_CT1 to J_CT4, pressure inputs J_PRESS1 / J_PRESS2, and test points TP9 / TP10.
Verified the project still enforces the intended rail split: board +3V3 exists for U2, U4, and U7, while the Heltec internal 3.3 V header pins on J_HELTEC_L remain separate.
Confirmed several previously completed nets are present: SDA, SCL, OW_DATA, ADC_CS, ADC_SCLK, ADC_MOSI, ADC_MISO, ADC_DRDY, ADC_SYNC, TMP_ALERT, FAN_CTRL, RELAY1_OUT to RELAY6_OUT, plus fused relay nets.
Confirmed the analog support parts needed for completion are already present, including R1 to R24, R39, R_BOOT45, R_BOOT46, R_SENSE1, R_SENSE2, C_F6P, C_F6N, and clamp diodes D1 to D6.
Identified a project-state inconsistency: the corrected connector components J_VIB1, J_VIB2, J_VIB3, J_AIN6, and J_FAN were expected from prior work, but direct schematic reads show they are not currently present, so rewiring them could not proceed.

Success criteria review

✅ Re-checked the current source-of-truth schematic state directly before making further edits.
✅ Verified that the main digital/control wiring and the board +3V3 versus Heltec internal 3.3 V separation are still intact around U2, U4, U7, and J_HELTEC_L.
❌ Could not complete the remaining schematic work because the required corrected connector bodies J_VIB1, J_VIB2, J_VIB3, J_AIN6, and J_FAN are missing from the live document state.
❌ Because those connectors are missing, I could not finish the mux branch wiring on U4, the spare analog input routing from J_AIN6 to U2, or the fan connector completion from U3.
❌ I also could not proceed to final ERC cleanup or the remaining PCB mechanical features because the schematic completion step is still blocked.

Next steps The next required step is to restore the missing corrected connector components in the live project state, then re-run the remaining wiring for U4, U2, and U3, followed by ERC and PCB mechanical completion. I was blocked from doing that here because project edits are no longer available in this session.

Started implementing a plan

Goal: Complete SCADA Sensor Node v2.1 schematic + PCB per KiCad reference and PCB_DESIGN_SPEC v2.1, preserving Heltec internal 3V3 isolation.

Completed so far:

- Parsed KiCad schematic reference + PCB design spec; extracted connector pinouts, ADC/mux/temp wiring, and mechanical/ground strategy.

- Set project metadata for dual-rail constraint (Heltec 3V3 pins must stay NC vs board +3V3 from U1 AP2112K-3.3).

- Set PCB baseline: 200 mm × 140 mm, 2-layer; recorded 1.6 mm thickness intent in properties.

- Schematic cleanup: removed legacy R53/R54; set R_SENSE1/R_SENSE2 to 47k/10k; added TP9/TP10; corrected TP4/TP5 metadata.

- Core digital wiring done: Heltec↔ADS131M08 SPI (CS/SCLK/MOSI/MISO/DRDY/SYNC), main I2C (SDA/SCL), OneWire (OW_DATA), relay GPIO (RELAY1–6), TMP102 ALERT→ULN2003A IN7 and ULN2003A O7=FAN_CTRL, relay outputs RELAYx_OUT.

- Removed incorrect connector variants and attempted to re-add correct J_VIB1/2/3, J_AIN6, J_FAN; however, tool state is inconsistent (designators not found after re-add), requiring reconciliation.

Implementation plan (remaining):

1. Reconcile connector desync: locate existing fan and vibration connectors currently present (e.g., the J_FAN referenced by net portals) and either rename them to J_VIB1/2/3, J_AIN6, J_FAN or re-add with unique designators; then verify with schematic query that the designators exist and pins match intended counts.

2. Wire vibration connectors to TCA9548A branches: connect each J_VIBx pin 1→+3V3, pin 2→GND, pin 3→MUX_SDAx, pin 4→MUX_SCLx; connect U4 channels 0–2 to MUX_SDA0/1/2 and MUX_SCL0/1/2; connect R19–R24 as 4.7k pullups to +3V3 on each branch SDA/SCL.

3. Complete TCA9548A configuration: connect U4 A0/A1/A2→GND and ~RESET→+3V3; mark unused channels 3–7 as intentional NC where appropriate.

4. Complete TMP102 configuration: connect U7 ADD0→GND (addr 0x48) and confirm ALERT pullup (R39=10k to +3V3) and TMP_ALERT net connectivity.

5. Finish ADS131M08 analog channel wiring per reference:

- Connect CT1–CT4 front ends (burden/bias/filter/clamp parts already present: R1–R4, R9–R16, C10–C13, D1–D4, VBIAS network R7/R8/C9) to U2 AIN0–AIN3 pins, and ensure test points TP4 etc. align with CTxN nodes.

- Connect pressure inputs J_PRESS1/2 via their series/filter/clamp networks to U2 AIN4P/AIN5P; tie AIN4N/AIN5N→GND.

- Connect spare diff input J_AIN6 to U2 AIN6P/AIN6N with any required filter caps (C_F6P/C_F6N) and keep TP9 on AIN6P.

- Connect 5V_SENSE divider (R_SENSE1/R_SENSE2) to U2 AIN7P with TP10; connect AIN7N→GND.

6. Verify/repair Heltec boot pulldowns: confirm R_BOOT45/R_BOOT46 are pulldowns to GND on the correct Heltec GPIO nets (currently appear associated with FLOW2_SIG and DIN2_SIG); rewire if needed to match “boot pulldown to GND” intent.

7. Run schematic completeness review: resolve remaining floating pins, explicitly mark intentional NC (Heltec NC pins 2–3 on J_HELTEC_L, unused mux channels), and ensure no orphan nets.

8. Implement PCB mechanical features in layout: add 4× M3 mounting holes (3.2 mm), 2× DIN slots (4.2×25 mm), and define Heltec keepout + antenna keepout regions.

9. Implement copper/ground strategy on PCB: bottom continuous GND plane; top GND pour; top-layer analog island around ADS131M08 with single star via at AGND pin; keep analog traces inside island and limit vias per spec.

10. Prepare for routing: place components (group analog front end around U2, keep mux branches near J_VIBx, keep fuses/relays near edge connectors); then instruct user to run Auto-Layout routing and perform airwire/DRC checks, fixing any issues found.

Task completed.

0:38

reconciling connector desync and wiring analogs...

4:57

Accessing knowledge.

Running 4 design checks.

Reading layout for J_VIB1, J_VIB2, J_VIB3 and 18 more...

Added 5 components

0:11

Added 4x 282837-4 as J_VIB1, J_VIB2, J_VIB3, J_AIN6 (Pins: 4, 3, 2, 1)

Added 1x 282837-3 as J_FAN (Pins: Pin_1, Pin_3, Pin_2)

Thought for 11 sec

flux

I found the connector desync root cause: the live schematic is missing the corrected J_VIB1, J_VIB2, J_VIB3, J_AIN6, and J_FAN. I am restoring them first with the correct field-terminal pin counts from the KiCad reference so the remaining mux and analog wiring can be applied cleanly.

Updating connections...

70d 14:21:06

Reviews

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Project Name

Description

SCADA Sensor Node v2.1 using a Heltec WiFi LoRa 32 V4 module with separate +5V and board-generated +3V3 rails, ADS131M08 8-channel ADC front end, TCA9548A I2C multiplexer, TMP102-based fan control, ULN2003A relay and fan driver, CT/pressure/analog/One-Wire/vibration/humidity/Qwiic/flow/digital sensor interfaces, relay outputs, fan connector, brownout sensing, and a 200 mm x 140 mm 2-layer layout with Heltec keepout, antenna clearance, mounting holes, and DIN-rail slots.

Properties

System Architecture

Diagram

Mechanic…straints

Board Thickness

Implemen… Details

Pricing & Availability

Distributor	Qty 1
Arrow	$32.64–$64.92
Digi-Key	$52.24–$55.44
LCSC	$50.86–$114.35
Mouser	$81.68–$163.15
TME	$49.71
Verical	$57.21–$198.97

Controls

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