RP2040-Zero Footprint Discussion

flux

Final manufacturing checklist passed for REV A: no open DRC/ERC issues in the checked categories, connector/pinout/power mapping verified, and I added the 5V NC / DO NOT USE silkscreen warning. The only caveat is BOM-only: the 22 bare copper test pads have no MPN, which is expected unless you want assembled test-point hardware.
Project files:
Exports:
Suggested next steps:
  1. Open the Gerber ZIP in JLCPCB/PCBWay viewer and visually confirm board outline, drills, silk, and connector pin-1 marks.
  2. Verify CPL rotations for the two FFC connectors before assembly order.
  3. Continuity-check one FFC cable/wing prototype against the connector-orientation note before powering.
Review exports and BOM
Check Gerber visuals
Verify CPL rotations
Clean BOM caveats
Create bring-up checklist
Sign up to send

Files

Pins

Symbol

Layout

Preview

TP_B
TP_LY
JRIGHT
TP_R2
TP_RX
TP_GND
TP_A
TP_START
TP_X
TP_L3
TP_RY
TP_DPAD_LEFT
TP_DPAD_UP
TP_SELECT
TP_R3
TP_DPAD_RIGHT
TP_L2
TP_LX
TP_3V3
TP_Y
TP_R1
TP_L1
JLEFT
TP_DPAD_DOWN
H1
H4
H2
U1
H3
Project Specification
Project Overview
  • Project: RP2040-Zero Controller Carrier
  • Status: Schematic build in progress
  • Scope: Central controller motherboard / Waveshare RP2040-Zero castellated carrier only.
  • Out of scope: Left/right wing boards, display board, USB hub board, battery board, power board, phone dock board, shell, Gerber export.
GPIO-Count Decision
HOME has been removed entirely from the controller design. The design now uses exactly 16 independent digital GPIO inputs plus 4 ADC inputs, matching the exposed Waveshare RP2040-Zero footprint: GP0-GP15 for digital inputs and GP26-GP29 for analog axes.
Do not add HOME, Guide, any extra system button, I/O expander, second MCU, alternate RP2040 module, or digital use of GP26-GP29. Keep only START and SELECT as system/navigation buttons.
Intended Use
Prototype central controller board for a clamshell dual-screen Android gaming dock. The board receives left/right controller wing signals over ribbon cables and sends USB gamepad data via the RP2040-Zero built-in USB-C port to an internal USB hub.
Main Features
  • Solder-mounted Waveshare RP2040-Zero module using castellated pads.
  • JLEFT and JRIGHT 14-pin 1.00 mm FFC/FPC connectors using Molex 0528081471 / 528081471.
  • Direct active-low independent GPIO inputs for every button signal.
  • Four analog stick axes routed only to RP2040 ADC-capable pins.
  • Duplicate labeled 2.54 mm debug/test pads for GND, 3V3, all digital signals, and all analog axes.
  • M2 NPTH mounting holes and optional cable strain relief holes/slots.
  • Board label: CONTROLLER CARRIER REV A.
Confirmed Connector Path
Preferred connector: Würth Elektronik 68611414422, 14-position 1.00 mm FFC/FPC right-angle/horizontal bottom-contact ZIF SMT. Flux library did not return this exact MPN.
Backup connector selected for implementation: Molex 0528081471 / 528081471, 14-position 1.00 mm FFC/FPC vertical SMD connector, Flux part UID 1dfde761-5f54-49cd-a196-cc691e705807, LCSC C277651. This preserves 14 positions and 1.00 mm pitch but changes entry style from right-angle to vertical.
Before routing, confirm the physical orientation details in layout: exact MPN used, pitch, contact side, FFC/FPC cable orientation, pin 1 direction, and vertical vs right-angle entry.
System Architecture
Diagram



  
    
  
  
    
  










JLEFT 14-pin 1.00 mm FFC/FPC
RP2040-Zero Carrier
JRIGHT 14-pin 1.00 mm FFC/FPC
Waveshare RP2040-Zero
Built-in USB-C to internal USB hub
Hardware Subsystems
Compute
  • Waveshare RP2040-Zero module.
  • Built-in USB-C remains accessible; no separate USB D+/D- connector unless absolutely required.
Input Connectors
  • JLEFT: 14-pin 1.00 mm FFC/FPC.
  • JRIGHT: 14-pin 1.00 mm FFC/FPC.
  • Pin-1 indicators and per-pin silkscreen labels required.
Power
  • Controller powered from phone through USB via RP2040-Zero USB-C.
  • 3V3 rail is sourced from RP2040-Zero 3V3 output to thumbstick modules on the wing boards.
  • No regulator, charger, boost converter, PD, battery, or power-management circuitry.
Debug/Test
  • Labeled duplicate 2.54 mm pads for all signals plus GND and 3V3.
  • Optional BOOT/RESET pads or buttons if module buttons become hard to access.
Interfaces and Connections
JLEFT Pinout

Table

PinNet
1GND
23V3
3DPAD_LEFT
4DPAD_DOWN
5DPAD_UP
6DPAD_RIGHT
7SELECT
8L1
9L2
10LX
11LY
12L3
13GND
14SPARE_LEFT / NC
JRIGHT Pinout

Table

PinNet
1GND
23V3
3A
4B
5X
6Y
7START
8R1
9R2
10RX
11RY
12R3
13GND
14SPARE_RIGHT / NC
Firmware-Relevant Hardware Requirements
Final Analog Mapping

Table

SignalRP2040 PadGPIO / ADC
LXGP26 / ADC0GP26 / ADC0
LYGP27 / ADC1GP27 / ADC1
RXGP28 / ADC2GP28 / ADC2
RYGP29 / ADC3GP29 / ADC3
Digital Inputs
Independent active-low GPIO inputs: DPAD_LEFT, DPAD_DOWN, DPAD_UP, DPAD_RIGHT, SELECT, L1, L2, L3, A, B, X, Y, START, R1, R2, R3.
Final Digital Mapping

Table

SignalConnector PinRP2040-Zero PadGPIO
DPAD_LEFTJLEFT pin 3GP0GP0
DPAD_DOWNJLEFT pin 4GP1GP1
DPAD_UPJLEFT pin 5GP2GP2
DPAD_RIGHTJLEFT pin 6GP3GP3
SELECTJLEFT pin 7GP4GP4
L1JLEFT pin 8GP5GP5
L2JLEFT pin 9GP6GP6
L3JLEFT pin 12GP7GP7
AJRIGHT pin 3GP8GP8
BJRIGHT pin 4GP9GP9
XJRIGHT pin 5GP10GP10
YJRIGHT pin 6GP11GP11
STARTJRIGHT pin 7GP12GP12
R1JRIGHT pin 8GP13GP13
R2JRIGHT pin 9GP14GP14
R3JRIGHT pin 12GP15GP15
Schematic Verification Status
  • HOME removed: confirmed.
  • Digital GPIO count: 16 independent digital inputs on GP0-GP15.
  • ADC count: 4 analog inputs on GP26-GP29.
  • JLEFT/JRIGHT connector part: Molex 0528081471 / 528081471, 14-position, 1.00 mm pitch FFC/FPC vertical SMD.
  • ERC status after schematic wiring: no open ERROR/WARNING checks for checked ERC categories; mounting holes marked no-connect.
Physical Design Expectations
  • Compact rectangular board preferred, under/behind the 7-inch display area.
  • Do not exceed about 160.91 mm x 89.13 mm unless necessary.
  • JLEFT toward left edge, JRIGHT toward right edge.
  • RP2040-Zero USB-C accessible from board edge/cutout.
  • Labels kept clear of pads and mounting holes.
Important Design Decisions
  • HOME removed to fit the exposed GPIO count.
  • No button matrix; every digital signal remains independent.
  • No external USB connector for D+/D-; use RP2040-Zero built-in USB-C.
  • No separate power circuit.
  • Preferred Würth connector unavailable in library; user-approved backup Molex 0528081471 is available and has been added for JLEFT/JRIGHT.
Assumptions
  • 2-layer PCB is acceptable unless routing/grounding review shows a need for 4 layers.
  • All components on top side unless mechanical constraints require otherwise.
Change Notes
  • Initial requirements captured from pasted project brief.
  • Project renamed and description updated.
  • Connector path updated: Molex 0528081471 backup selected and added.
  • HOME removed per user decision; GPIO-count blocker resolved.

  • Project Overview

  • GPIO-Count Decision

  • Intended Use

  • Main Features

  • Confirmed Connector Path

  • System Architecture

  • Hardware Subsystems

  • Compute

  • Input Connectors

  • Power

  • Debug/Test

  • Interfaces and Connections

  • JLEFT Pinout

  • JRIGHT Pinout

  • Firmware-Relevant Hardware Requirements

  • Final Analog Mapping

  • Digital Inputs

  • Final Digital Mapping

  • Schematic Verification Status

  • Physical Design Expectations

  • Important Design Decisions

  • Assumptions

  • Change Notes