Project Definition Brainstorming
Started implementing a plan
High-level goal: Design a compact inline “AI calculator cable” PCB using ESP32-S3-WROOM-1-N16R8, powered from USB-C 5V into AP2112K-3.3, and communicating USB 2.0 to a TI-Nspire CX II via hardwired mini-USB OTG (ID tied to GND). Finalize schematic + PCB so it is fully routed, DRC/E RC clean, and ready for JLCPCB assembly outputs.
What has been completed:
- Schematic created with required blocks: ESP32-S3-WROOM-1-N16R8 (native USB), USB-C 2.0 receptacle (J1) with 5.1k Rd on CC1/CC2, AP2112K-3.3TRG1 LDO (U2) with EN tied to VIN, input/output 10uF caps, multiple 0.1uF decouplers + optional 1uF near ESP32, USBLC6-2SC6 ESD (D1) on D+/D-, hardwired mini-USB (J2 UX60SC-MB-5ST(80)) with ID to GND for OTG host mode, BOOT and RESET/EN buttons, and a status LED + resistor.
- PCB layout initialized: 70 mm x 22 mm, 4-layer stackup; initial placement with J1 and J2 at opposite ends and ESP32 near an edge; project documentation added (esp32-s3-ai-calculator-cable-design-notes).
- Baseline layout rules updated for manufacturability (minTraceWidth 0.15 mm; preferred widths 0.15/0.25/0.4 mm).
- DRC status checked: outstanding errors include 34 airwires (unrouted nets) and 2 overlapping-copper violations (likely around SW1/SW2); no dangling-trace issues were reported in the last review.
Implementation plan (remaining work only):
1. Fix DRC overlap errors
1. Identify the exact copper/features causing the 2 overlapping-copper violations.
2. Adjust PCB placement of the offending parts (likely SW1/SW2) to eliminate pad/copper overlap while keeping the inline form factor.
3. Re-run DRC for overlapping copper to confirm it is cleared.
2. Placement optimization for routing and RF keepout
1. Re-pack components to fit within 70 mm x 22 mm (or slightly resize if needed) so the aggregate component bounds do not exceed the board.
2. Ensure ESP32 antenna edge placement and keepout (no copper/pours/components under antenna on all layers).
3. Place decoupling caps tight to ESP32 3V3/GND pins and keep USBLC6 close to the USB data path.
3. Complete PCB routing
1. Route power first (VBUS_5V to U2 VIN; U2 VOUT/3V3 to ESP32 3V3 pins) with wider traces; ensure solid return paths to GND.
2. Route USB differential pair (USB_DP/USB_DM) short, coupled, length-matched, and with minimal vias; keep ESD close to connector/entry.
3. Route remaining low-speed signals (BOOT, EN/RESET, LED) and any remaining nets.
4. Add/verify GND copper fills and stitching as appropriate while respecting antenna keepout.
4. Iterate validation to DRC/ERC clean
1. Re-run DRC (airwires, overlap, clearance) until 0 errors.
2. Re-run ERC checks for floating/undriven pins or single-pin nets and fix any schematic issues found.
5. Manufacturing preparation for JLCPCB assembly
1. Verify all parts have correct footprints and MPNs where required; ensure passives have values and package sizes.
2. Update design notes with final routing guidance, OTG wiring notes, enclosure/strain-relief guidance, and assembly notes.
3. Export Gerbers, BOM, and pick-and-place (CPL) for JLCPCB; optionally export STEP for enclosure fit-check.
Execution stopped due to insufficient credits.
0:19
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