Project Definition Brainstorming

flux

Work done
  • I cannot make additional project edits in this session because execution credits are exhausted.
  • Current known project state from the brief: schematic is already created with the required ESP32-S3, USB-C power/flashing, AP2112K 3.3 V regulator, USBLC6 USB ESD, hardwired mini-USB OTG with ID tied to GND, BOOT/RESET buttons, LED, and decoupling.
  • PCB is initialized as a compact 70 mm x 22 mm 4-layer inline board with baseline manufacturable rules already set.
Success criteria review
  • ✅ Schematic blocks are present.
  • ✅ Board outline, stackup, initial placement, and baseline trace rules are present.
  • ❌ PCB is not finished yet: 34 airwires remain.
  • ❌ DRC is not clean yet: 2 overlapping-copper violations remain, likely around SW1/SW2.
  • ❌ JLCPCB outputs should not be generated until routing and DRC/ERC cleanup are complete.
Next steps
Resume with a work-capable session to finish the product: fix SW1/SW2 copper overlap, repack placement while preserving ESP32 antenna keepout, route power/USB/low-speed nets, iterate DRC/ERC to zero actionable errors, update the design notes, then export Gerbers, BOM, CPL/pick-and-place, and optionally STEP for JLCPCB/enclosure fit-check.
J1
U2
D1
R2
Resistance
5.1 kΩ
R5
Resistance
1 kΩ
R1
Resistance
5.1 kΩ
R4
Resistance
10 kΩ
R3
Resistance
10 kΩ
C3
Capacitance
0.1 µF
C5
Capacitance
1 µF
C1
Capacitance
10 µF
C6
Capacitance
0.1 µF
C4
Capacitance
0.1 µF
C2
Capacitance
10 µF
SW2
J1 VBUS - U2 VIN
J1 D+ - J2 3
SW1
U1 IO0 - R4 P2
U2 VOUT - U1 3V3
U1 IO48 - R5 P1
J1 CC2 - R2 P1
U2 VOUT - U1 3V3
R5 P2 - LED1 A
U1 EN - R3 P2
U2 VOUT - U1 3V3
U1 EN - R3 P2
J1 D- - J2 2
J1 D- - J2 2
J1 D+ - J2 3
U1 IO48 - R5 P1
J1 D- - J2 2
U2 VOUT - U1 3V3
U1 IO0 - R4 P2
J1 CC1 - R1 P1
U2 EN - C1 P1
U2 VOUT - U1 3V3
J1 CC2 - R2 P1
U2 VOUT - U1 3V3
U2 EN - C1 P1
J1 D- - J2 2
U1 EN - R3 P2
U2 VOUT - U1 3V3
J1 D+ - J2 3
U1 IO0 - R4 P2
U1 EN - R3 P2
U2 EN - C1 P1
J1 VBUS - U2 VIN
R5 P2 - LED1 A
J1 CC1 - R1 P1
J1 D+ - J2 3
U2 VOUT - U1 3V3
U2 EN - C1 P1
GND
J1 GND - D1 GND
GND
J2 4 - C1 P2
J2 4 - C1 P2
U1 GND - U2 GND
J2 4 - C1 P2
U1 GND - U2 GND
J2 4 - C1 P2
J2 4 - C1 P2
J1 GND - D1 GND
J2 4 - C1 P2
J2 4 - C1 P2
J2 4 - C1 P2
J2 4 - C1 P2
J2 4 - C1 P2
U1 GND - U2 GND
J1 GND - D1 GND
J2 4 - C1 P2
J2 4 - C1 P2
U1
LED1
J2

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ESP32-S3 AI Calculator Cable Design Notes
Architecture
  • Core MCU: ESP32-S3-WROOM-1-N16R8 (U1), powered from regulated 3V3.
  • USB-C connector (J1) provides 5 V input (VBUS_5V) and a shared native USB data path for flashing/debug use.
  • AP2112K-3.3TRG1 (U2) converts VBUS_5V to 3V3; EN is tied to VIN for always-on operation.
  • USBLC6-2SC6 (D1) protects USB_DP and USB_DM.
  • Mini-USB OTG endpoint (J2) represents the hardwired mini-USB male pigtail to the TI-Nspire CX II. Pin 4 / ID is tied to GND to force host/OTG behavior on the calculator side.
  • BOOT (SW1) pulls ESP32 IO0 low; RESET (SW2) pulls EN low.
  • Status LED (LED1) is driven from ESP32 IO48 through R5.
Key Nets
  • VBUS_5V: USB-C VBUS, AP2112K VIN/EN, USBLC6 VBUS reference, mini-USB VBUS reference.
  • 3V3: AP2112K VOUT to ESP32 3V3, pull-ups, and decoupling.
  • USB_DP: J1 D+, J2 D+, USBLC6 I/O1 pair, ESP32 IO20.
  • USB_DM: J1 D-, J2 D-, USBLC6 I/O2 pair, ESP32 IO19.
  • ESP_BOOT: ESP32 IO0, 10 kΩ pull-up, BOOT switch to GND.
  • ESP_EN: ESP32 EN, 10 kΩ pull-up, RESET switch to GND, 100 nF filter capacitor.
  • STATUS_LED: ESP32 IO48 to R5 and LED1.
Component Choices
  • ESP32 module uses LCSC/JLCPCB-supported ESP32-S3-WROOM-1-N16R8.
  • Passives are assigned JLCPCB-friendly MPN/LCSC metadata:
    • 5.1 kΩ CC pull-downs: Yageo RC0402FR-075K1L / C25905.
    • 10 kΩ pull-ups: Yageo RC0402FR-0710KL / C25744.
    • 1 kΩ LED resistor: Yageo RC0402FR-071KL / C11702.
    • 10 µF capacitors: Samsung CL10A106KP8NNNC / C19702.
    • 100 nF capacitors: Samsung CL05B104KO5NNNC / C1525.
    • 1 µF capacitor: Samsung CL05A105KA5NQNC / C52923.
Layout Setup
  • Board outline: 70 mm x 22 mm rectangle with 1.5 mm corner radius.
  • Stackup: Standard 4-layer custom stackup, layer 2 as ground reference, layer 3 as power plane.
  • Board inset / universal keepout: 0.15 mm.
  • Placement strategy:
    • J1 USB-C at left edge.
    • J2 mini-USB cable endpoint at right edge.
    • U1 ESP32-S3 at top edge with antenna facing outward and approximately 6 mm overhang/keepout intent.
    • U2 and input/output capacitors near J1.
    • D1 in the USB routing channel between connectors and ESP32 USB pins.
    • BOOT/RESET support parts near U1 pins.
    • LED along bottom edge for visibility.
Routing Guidance / Remaining Manual Step
The schematic and component placement are complete. Routing must keep USB_DP and USB_DM short, adjacent, and length-matched as practical, with a 90 Ω differential-pair target on the selected 4-layer JLCPCB stackup. Keep copper and components out from under the ESP32 antenna region. Route power first (VBUS_5V, 3V3, GND), then USB differential pair, then low-speed BOOT/EN/LED nets.
Verification Notes
  • ERC intentional floating GPIO warnings were resolved by marking unused ESP32 pins as no-connect.
  • Current board still reports airwires because traces have not been physically routed.
  • Placement completed with connectors on opposite short edges and no placement overlap/out-of-bounds issues reported by the placement pass.

  • Architecture

  • Key Nets

  • Component Choices

  • Layout Setup

  • Routing Guidance / Remaining Manual Step

  • Verification Notes

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ESP32-S3 AI Calculator Cable

ESP32-S3 AI Calculator Cable thumbnail
Compact inline ESP32-S3 USB-C powered OTG cable interface for TI-Nspire CX II calculators

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$0.75–$1.40

Digi-Key

$6.34–$8.76

HQonline

$2.05–$2.15

LCSC

$8.41–$8.57

Mouser

$11.58

TME

$1.67

Verical

$1.80–$33.28

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